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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-08 20:30:02 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-21 08:50:26 +0800 |
| commit | 3ff1b5f1c6c6e13777be1c677abc2340f3dabd1a (patch) | |
| tree | b5c4481531b8da56e2aa4ef5473c148ef0b9f177 /riscv/clint.cc | |
| parent | 28ee0c4d6a1ed221f1a05ba48f54023ac7d455cc (diff) | |
| download | spike-3ff1b5f1c6c6e13777be1c677abc2340f3dabd1a.zip spike-3ff1b5f1c6c6e13777be1c677abc2340f3dabd1a.tar.gz spike-3ff1b5f1c6c6e13777be1c677abc2340f3dabd1a.tar.bz2 | |
add support for time/timeh/htimedelta/htimedeltah csrs
Diffstat (limited to 'riscv/clint.cc')
| -rw-r--r-- | riscv/clint.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/clint.cc b/riscv/clint.cc index 72d1bbe..3f2d4d7 100644 --- a/riscv/clint.cc +++ b/riscv/clint.cc @@ -82,6 +82,7 @@ void clint_t::increment(reg_t inc) mtime += inc; } for (size_t i = 0; i < procs.size(); i++) { + procs[i]->state.time->sync(mtime); procs[i]->state.mip->backdoor_write_with_mask(MIP_MTIP, 0); if (mtime >= mtimecmp[i]) procs[i]->state.mip->backdoor_write_with_mask(MIP_MTIP, MIP_MTIP); |