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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-02-15 01:24:19 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-02-15 01:24:19 -0800 |
| commit | 6d68f47aec9578a9a5d7f0476f49ded6df79932b (patch) | |
| tree | 1442b37f995d2976487bd91adac5af153c7ee3bb /riscv/cachesim.h | |
| parent | 290c702c0f70973d9a34f837ca9b71a5765a81c6 (diff) | |
| download | spike-6d68f47aec9578a9a5d7f0476f49ded6df79932b.zip spike-6d68f47aec9578a9a5d7f0476f49ded6df79932b.tar.gz spike-6d68f47aec9578a9a5d7f0476f49ded6df79932b.tar.bz2 | |
fix D$ model not acknowledging stores
Diffstat (limited to 'riscv/cachesim.h')
| -rw-r--r-- | riscv/cachesim.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/cachesim.h b/riscv/cachesim.h index d6f5946..d5dcf38 100644 --- a/riscv/cachesim.h +++ b/riscv/cachesim.h @@ -115,7 +115,7 @@ class dcache_sim_t : public cache_memtracer_t } void trace(uint64_t addr, size_t bytes, bool store, bool fetch) { - if (!fetch) cache->access(addr, bytes, false); + if (!fetch) cache->access(addr, bytes, store); } }; |