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authorAndrew Waterman <waterman@cs.berkeley.edu>2015-09-24 14:40:40 -0700
committerAndrew Waterman <waterman@cs.berkeley.edu>2015-09-24 18:10:00 -0700
commit3258ff6431d22da76bd1cd873789a6c82d0af3b0 (patch)
treef1dd616f8a739d0fb418dfe8442a94720e5a88cf /riscv/cachesim.h
parent7959893ef66cce47b92f73d797d9ee5144d16f60 (diff)
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Use enum instead of two bools to denote memory access type
Diffstat (limited to 'riscv/cachesim.h')
-rw-r--r--riscv/cachesim.h16
1 files changed, 8 insertions, 8 deletions
diff --git a/riscv/cachesim.h b/riscv/cachesim.h
index a529007..d597f79 100644
--- a/riscv/cachesim.h
+++ b/riscv/cachesim.h
@@ -97,13 +97,13 @@ class icache_sim_t : public cache_memtracer_t
{
public:
icache_sim_t(const char* config) : cache_memtracer_t(config, "I$") {}
- bool interested_in_range(uint64_t begin, uint64_t end, bool store, bool fetch)
+ bool interested_in_range(uint64_t begin, uint64_t end, access_type type)
{
- return fetch;
+ return type == FETCH;
}
- void trace(uint64_t addr, size_t bytes, bool store, bool fetch)
+ void trace(uint64_t addr, size_t bytes, access_type type)
{
- if (fetch) cache->access(addr, bytes, false);
+ if (type == FETCH) cache->access(addr, bytes, false);
}
};
@@ -111,13 +111,13 @@ class dcache_sim_t : public cache_memtracer_t
{
public:
dcache_sim_t(const char* config) : cache_memtracer_t(config, "D$") {}
- bool interested_in_range(uint64_t begin, uint64_t end, bool store, bool fetch)
+ bool interested_in_range(uint64_t begin, uint64_t end, access_type type)
{
- return !fetch;
+ return type == LOAD || type == STORE;
}
- void trace(uint64_t addr, size_t bytes, bool store, bool fetch)
+ void trace(uint64_t addr, size_t bytes, access_type type)
{
- if (!fetch) cache->access(addr, bytes, store);
+ if (type == LOAD || type == STORE) cache->access(addr, bytes, type == STORE);
}
};