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author | liweiwei <liweiwei@iscas.ac.cn> | 2021-12-30 16:31:54 +0800 |
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committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-01-29 17:22:40 +0800 |
commit | 456913b2c97d55993103594991a7ac73453465f8 (patch) | |
tree | 7d15559ab7f5641b62d32c045a82f00c13c909a3 /riscv/cachesim.cc | |
parent | 14e54ebb9359d6dd1e41b54ca94dc034d3bfd577 (diff) | |
download | spike-456913b2c97d55993103594991a7ac73453465f8.zip spike-456913b2c97d55993103594991a7ac73453465f8.tar.gz spike-456913b2c97d55993103594991a7ac73453465f8.tar.bz2 |
add clean_invalidate function for caches
Diffstat (limited to 'riscv/cachesim.cc')
-rw-r--r-- | riscv/cachesim.cc | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/riscv/cachesim.cc b/riscv/cachesim.cc index 6e030d1..48840cb 100644 --- a/riscv/cachesim.cc +++ b/riscv/cachesim.cc @@ -159,6 +159,31 @@ void cache_sim_t::access(uint64_t addr, size_t bytes, bool store) *check_tag(addr) |= DIRTY; } +void cache_sim_t::clean_invalidate(uint64_t addr, size_t bytes, bool clean, bool inval) +{ + uint64_t start_addr = addr & ~(linesz-1); + uint64_t end_addr = (addr + bytes + linesz-1) & ~(linesz-1); + uint64_t cur_addr = start_addr; + while (cur_addr < end_addr) { + uint64_t* hit_way = check_tag(cur_addr); + if (likely(hit_way != NULL)) + { + if (clean) { + if (*hit_way & DIRTY) { + writebacks++; + *hit_way &= ~DIRTY; + } + } + + if (inval) + *hit_way &= ~VALID; + } + cur_addr += linesz; + } + if (miss_handler) + miss_handler->clean_invalidate(addr, bytes, clean, inval); +} + fa_cache_sim_t::fa_cache_sim_t(size_t ways, size_t linesz, const char* name) : cache_sim_t(1, ways, linesz, name) { |