Add "--log-cache-miss" option to generate a log of cache miss. (#241)

* Add "--log-cache-miss" option to generate a log of cache miss.

- This option must be used with "--ic" and/or "--dc" options
  to enable cache simulation.
- This option is useful with "-l" option to understand
  which instruction has caused the cache miss.

* Modify log format of cache miss to reduce log size.

1 files changed, 8 insertions, 2 deletions

diff --git a/riscv/cachesim.cc b/riscv/cachesim.cc
index 90ab5be..6e030d1 100644
--- a/riscv/cachesim.cc
+++ b/riscv/cachesim.cc
@@ -7,7 +7,7 @@
 #include <iomanip>
 
 cache_sim_t::cache_sim_t(size_t _sets, size_t _ways, size_t _linesz, const char* _name)
- : sets(_sets), ways(_ways), linesz(_linesz), name(_name)
+: sets(_sets), ways(_ways), linesz(_linesz), name(_name), log(false)
 {
   init();
 }
@@ -62,7 +62,7 @@ void cache_sim_t::init()
 
 cache_sim_t::cache_sim_t(const cache_sim_t& rhs)
  : sets(rhs.sets), ways(rhs.ways), linesz(rhs.linesz),
-   idx_shift(rhs.idx_shift), name(rhs.name)
+   idx_shift(rhs.idx_shift), name(rhs.name), log(false)
 {
   tags = new uint64_t[sets*ways];
   memcpy(tags, rhs.tags, sets*ways*sizeof(uint64_t));
@@ -135,6 +135,12 @@ void cache_sim_t::access(uint64_t addr, size_t bytes, bool store)
   }
 
   store ? write_misses++ : read_misses++;
+  if (log)
+  {
+    std::cerr << name << " "
+              << (store ? "write" : "read") << " miss 0x"
+              << std::hex << addr << std::endl;
+  }
 
   uint64_t victim = victimize(addr);