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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-08 21:45:32 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-10 00:30:07 -0700 |
| commit | e219277150687c391a1af3d6b6117b5c1813eaec (patch) | |
| tree | 1cf69eb89f822e2b094fc5c0cda1e443ac570aec /fesvr | |
| parent | 38802a0ad4984b533a3a558de2b347de5cfaa425 (diff) | |
| download | spike-e219277150687c391a1af3d6b6117b5c1813eaec.zip spike-e219277150687c391a1af3d6b6117b5c1813eaec.tar.gz spike-e219277150687c391a1af3d6b6117b5c1813eaec.tar.bz2 | |
op: update CSR
1. add new hypervisor csr
2. add debug module csr
3. add some new high part register for rv32
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'fesvr')
| -rw-r--r-- | fesvr/dtm.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/fesvr/dtm.cc b/fesvr/dtm.cc index 993011d..91cacb2 100644 --- a/fesvr/dtm.cc +++ b/fesvr/dtm.cc @@ -433,11 +433,11 @@ uint64_t dtm_t::modify_csr(unsigned which, uint64_t data, uint32_t type) // need to run more commands to save and restore // S0. uint32_t prog[] = { - CSRRx(WRITE, S0, CSR_DSCRATCH, S0), + CSRRx(WRITE, S0, CSR_DSCRATCH0, S0), LOAD(xlen, S0, X0, data_base), CSRRx(type, S0, which, S0), STORE(xlen, S0, X0, data_base), - CSRRx(WRITE, S0, CSR_DSCRATCH, S0), + CSRRx(WRITE, S0, CSR_DSCRATCH0, S0), EBREAK }; |