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| author | Megan Wachs <megan@sifive.com> | 2020-02-10 09:37:40 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-02-12 23:08:01 -0800 |
| commit | a0cb7e458f2577f3524632d6f48ad00090fdfbfe (patch) | |
| tree | 7fbcaa0c8d45dcaf367002a156ffcf6d9b82e9d7 /fesvr | |
| parent | 852fe0047a937fdc943f358f726e28b1ae62dd6b (diff) | |
| download | spike-a0cb7e458f2577f3524632d6f48ad00090fdfbfe.zip spike-a0cb7e458f2577f3524632d6f48ad00090fdfbfe.tar.gz spike-a0cb7e458f2577f3524632d6f48ad00090fdfbfe.tar.bz2 | |
FESVR: Can't read a DM register when DMACTIVE=0
Diffstat (limited to 'fesvr')
| -rw-r--r-- | fesvr/dtm.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fesvr/dtm.cc b/fesvr/dtm.cc index 5409321..46032c3 100644 --- a/fesvr/dtm.cc +++ b/fesvr/dtm.cc @@ -137,7 +137,7 @@ void dtm_t::resume(int hartsel) current_hart = hartsel; if (running) { - write(DMI_DMCONTROL, 0); + write(DMI_DMCONTROL, DMI_DMCONTROL_DMACTIVE); // Read dmstatus to avoid back-to-back writes to dmcontrol. read(DMI_DMSTATUS); } |