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author | Ben Marshall <ben.marshall@bristol.ac.uk> | 2021-02-18 13:22:45 +0000 |
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committer | Ben Marshall <ben.marshall@bristol.ac.uk> | 2021-02-18 13:22:45 +0000 |
commit | 5730d12167e0a0834d14b6332a4dd31d673bf73b (patch) | |
tree | 3201a091a755ec93d69f93d83b9a5e7c096c607e /disasm | |
parent | 8faa928819fb551325e76b463fc0c978e22f5be3 (diff) | |
download | spike-5730d12167e0a0834d14b6332a4dd31d673bf73b.zip spike-5730d12167e0a0834d14b6332a4dd31d673bf73b.tar.gz spike-5730d12167e0a0834d14b6332a4dd31d673bf73b.tar.bz2 |
scalar-crypto: Fix RV32 sha512 instructions.
These instructions are RV32 only. Previously, they zero-extended
their 32-bit result to 64-bits, to match the Spike implementation detail
that the X registers are always 64-bits long.
This exposed a data dependant problem when the instruction results fed
into the add and sltu instructions. The lack of sign extension on the
sha512*, combined with the presence of sign extension on the add, meant
sltu would (as it is currently implemented) produce the wrong result.
There were two potential fixes:
1) Sign extend from 32-bits to XLEN the result of the SHA512 instructions.
2) Change the SLTU implementation to truncate RS1/RS2 to be XLEN bits
before it does the comparison.
This patch implements option 1, because I didn't want to mess with a
base ISA instruction. However, this leaves the implementation detail
open to cause problems for people in the future. Fixing this is outside
the scope of this commit.
On branch scalar-crypto-fix
Changes to be committed:
modified: riscv/insns/sha512sig0h.h
modified: riscv/insns/sha512sig0l.h
modified: riscv/insns/sha512sig1h.h
modified: riscv/insns/sha512sig1l.h
modified: riscv/insns/sha512sum0r.h
modified: riscv/insns/sha512sum1r.h
Diffstat (limited to 'disasm')
0 files changed, 0 insertions, 0 deletions