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| author | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
| commit | 68aeeb5500521ff52c216862f9a653b64191f3ad (patch) | |
| tree | 407230ff48f79f177a792451598d9b2b6e3d34a0 /debug_rom | |
| parent | 191634d2854dfed448fc323195f9b65c305e2d77 (diff) | |
| parent | 03be4ae6c7b8e9865083b61427ff9724c7706fcf (diff) | |
| download | spike-68aeeb5500521ff52c216862f9a653b64191f3ad.zip spike-68aeeb5500521ff52c216862f9a653b64191f3ad.tar.gz spike-68aeeb5500521ff52c216862f9a653b64191f3ad.tar.bz2 | |
Merge branch 'master' into plic_uart_v1plic_uart_v1
Diffstat (limited to 'debug_rom')
| -rw-r--r-- | debug_rom/Makefile | 2 | ||||
| -rwxr-xr-x | debug_rom/debug_rom.S | 8 |
2 files changed, 5 insertions, 5 deletions
diff --git a/debug_rom/Makefile b/debug_rom/Makefile index c5f2205..d6546e9 100644 --- a/debug_rom/Makefile +++ b/debug_rom/Makefile @@ -18,7 +18,7 @@ all: $(patsubst %,%.h,$(ELFS)) $(OBJCOPY) -O binary --only-section .text $^ $@ debug_rom: $(DEPS) - $(COMPILE) -o $@ $^ + $(COMPILE) -o $@ $< clean: rm -f $(ELFS) debug_rom*.raw debug_rom.h diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S index 8d8e4cd..2d36139 100755 --- a/debug_rom/debug_rom.S +++ b/debug_rom/debug_rom.S @@ -23,7 +23,7 @@ _entry: // This fence is required because the execution may have written something // into the Abstract Data or Program Buffer registers. fence - csrw CSR_DSCRATCH, s0 // Save s0 to allow signaling MHARTID + csrw CSR_DSCRATCH0, s0 // Save s0 to allow signaling MHARTID // We continue to let the hart know that we are halted in order that // a DM which was reset is still made aware that a hart is halted. @@ -46,14 +46,14 @@ _exception: // Restore S0, which we always save to dscratch. // We need this in case the user tried an abstract write to a // non-existent CSR. - csrr s0, CSR_DSCRATCH + csrr s0, CSR_DSCRATCH0 sw zero, DEBUG_ROM_EXCEPTION(zero) // Let debug module know you got an exception. ebreak going: csrr s0, CSR_MHARTID sw s0, DEBUG_ROM_GOING(zero) // When debug module sees this write, the GO flag is reset. - csrr s0, CSR_DSCRATCH // Restore s0 here + csrr s0, CSR_DSCRATCH0 // Restore s0 here fence fence.i jalr zero, zero, %lo(whereto) // Debug module will put different instructions and data in the RAM, @@ -63,7 +63,7 @@ going: _resume: csrr s0, CSR_MHARTID sw s0, DEBUG_ROM_RESUMING(zero) // When Debug Module sees this write, the RESUME flag is reset. - csrr s0, CSR_DSCRATCH // Restore s0 + csrr s0, CSR_DSCRATCH0 // Restore s0 dret // END OF ACTUAL "ROM" CONTENTS. BELOW IS JUST FOR LINKER SCRIPT. |