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| author | Tim Newsome <tim@sifive.com> | 2016-05-01 13:18:03 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:11 -0700 |
| commit | 8e418f9e54a3a0d8f15b75ad1ad43ae925fea7e0 (patch) | |
| tree | 368edbc6473dc32d0a9e0c722bc204ce681b0d31 /debug_rom/debug_rom.S | |
| parent | cb73c085a22b225576b5d5c22f74490f9e30a5a8 (diff) | |
| download | spike-8e418f9e54a3a0d8f15b75ad1ad43ae925fea7e0.zip spike-8e418f9e54a3a0d8f15b75ad1ad43ae925fea7e0.tar.gz spike-8e418f9e54a3a0d8f15b75ad1ad43ae925fea7e0.tar.bz2 | |
Implement single memory read access.
Prevent unaligned accesses in memory read.
Also change how exceptions in Debug Mode are signaled.
Diffstat (limited to 'debug_rom/debug_rom.S')
| -rwxr-xr-x | debug_rom/debug_rom.S | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S index b1fa8bd..35dd406 100755 --- a/debug_rom/debug_rom.S +++ b/debug_rom/debug_rom.S @@ -29,15 +29,14 @@ entry: j _entry resume: j _resume exception: - # Flip the LSB of the first word in Debug RAM so the debugger can know - # that we hit an exception. - lw s1, (DEBUG_RAM)(zero) - xori s1, s1, 1 - sw s1, (DEBUG_RAM)(zero) - - # Fall through to resume. + # Set the last word of Debug RAM to all ones, to indicate that we hit + # an exception. + li s0, ~0 + j _resume2 _resume: + li s0, 0 +_resume2: # Clear debug interrupt. csrr s1, CSR_MHARTID sw s1, CLEARDEBINT(zero) @@ -58,6 +57,11 @@ restore_64: restore_128: nop #lq s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero) + # s0 contains ~0 if we got here through an exception, and 0 otherwise. + # Store this to the last word in Debug RAM so the debugger can tell if + # an exception occurred. + sw s0, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero) + check_halt: csrr s0, DCSR andi s0, s0, (1<<DCSR_HALT_OFFSET) @@ -68,7 +72,7 @@ exit: # Restore s0. csrr s0, DSCRATCH # TODO: dret? - mret + sret _entry: |