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| author | Tim Newsome <tim@sifive.com> | 2019-07-16 13:29:45 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-16 13:29:45 -0700 |
| commit | 3f200ac315c53d8caae1e454c19b655e6b35048b (patch) | |
| tree | 4b65fa7d0d1cefe9e41416e6864c04ca1607ae4a /debug_rom/debug_rom.S | |
| parent | b1bde2b904cd681c902d7c42c34bc55b4f4922ac (diff) | |
| download | spike-3f200ac315c53d8caae1e454c19b655e6b35048b.zip spike-3f200ac315c53d8caae1e454c19b655e6b35048b.tar.gz spike-3f200ac315c53d8caae1e454c19b655e6b35048b.tar.bz2 | |
Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)
* Don't corrupt s0 when abstract CSR write fails.
* Support abstract FPR access then mstatus.FS=0
Discussion on the spec list leans towards this being a requirement.
Certainly users want their debugger to be able to access all registers
regardless of target state.
Diffstat (limited to 'debug_rom/debug_rom.S')
| -rwxr-xr-x | debug_rom/debug_rom.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S index 03df533..8d8e4cd 100755 --- a/debug_rom/debug_rom.S +++ b/debug_rom/debug_rom.S @@ -43,6 +43,10 @@ entry_loop: jal zero, entry_loop _exception: + // Restore S0, which we always save to dscratch. + // We need this in case the user tried an abstract write to a + // non-existent CSR. + csrr s0, CSR_DSCRATCH sw zero, DEBUG_ROM_EXCEPTION(zero) // Let debug module know you got an exception. ebreak |