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| author | Tim Newsome <tim@sifive.com> | 2016-06-09 10:18:32 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2016-06-09 10:18:32 -0700 |
| commit | 1ec78cfedd16abb0095f9e77f2700af24522345d (patch) | |
| tree | 6044dc36db88506a73efdb9ae4f55683f966d820 /debug_rom/debug_rom.S | |
| parent | f82d42cdefb72f23a5a98b7d93413caec7bf5c8d (diff) | |
| download | spike-1ec78cfedd16abb0095f9e77f2700af24522345d.zip spike-1ec78cfedd16abb0095f9e77f2700af24522345d.tar.gz spike-1ec78cfedd16abb0095f9e77f2700af24522345d.tar.bz2 | |
Fix 2 bugs in Debug ROM: (#52)
1. Debug ROM wasn't actually writing 0xffffffff to the last word in
Debug RAM after an exception happened.
2. Fix a race where debug interrupts were cleared before that write
would have happened, so a debugger (gdbserver.cc in this case) might get
the wrong idea about whether an exception happened or not.
Why wasn't this wreaking havoc before?
Diffstat (limited to 'debug_rom/debug_rom.S')
| -rwxr-xr-x | debug_rom/debug_rom.S | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S index 9e83098..b0be7fc 100755 --- a/debug_rom/debug_rom.S +++ b/debug_rom/debug_rom.S @@ -30,9 +30,6 @@ exception: _resume: li s0, 0 _resume2: - # Clear debug interrupt. - csrr s1, CSR_MHARTID - sw s1, CLEARDEBINT(zero) fence # Restore s1. @@ -40,21 +37,26 @@ _resume2: bltz s1, restore_not_32 restore_32: lw s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero) - j check_halt + j finish_restore restore_not_32: slli s1, s1, 1 bltz s1, restore_128 restore_64: ld s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 8)(zero) - j check_halt + j finish_restore restore_128: nop #lq s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero) +finish_restore: # s0 contains ~0 if we got here through an exception, and 0 otherwise. # Store this to the last word in Debug RAM so the debugger can tell if # an exception occurred. sw s0, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero) + # Clear debug interrupt. + csrr s0, CSR_MHARTID + sw s0, CLEARDEBINT(zero) + check_halt: csrr s0, CSR_DCSR andi s0, s0, DCSR_HALT |