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| author | Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU> | 2011-04-15 14:32:54 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU> | 2011-04-15 14:33:12 -0700 |
| commit | 481c9e8fd8a89106f70b73b6bd62e08f5b1e688a (patch) | |
| tree | 4551a5e0246bab24823f3caac4cd1a8b66782011 /config.h.in | |
| parent | 402b4e8600281cb793bba0e493b37989a0db917f (diff) | |
| download | spike-481c9e8fd8a89106f70b73b6bd62e08f5b1e688a.zip spike-481c9e8fd8a89106f70b73b6bd62e08f5b1e688a.tar.gz spike-481c9e8fd8a89106f70b73b6bd62e08f5b1e688a.tar.bz2 | |
[sim] added icache simulator (disabled by default)
Diffstat (limited to 'config.h.in')
| -rw-r--r-- | config.h.in | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/config.h.in b/config.h.in index e592810..cf21aff 100644 --- a/config.h.in +++ b/config.h.in @@ -27,6 +27,9 @@ /* Define if floating-point instructions are supported */ #undef RISCV_ENABLE_FPU +/* Define if instruction cache simulator is enabled */ +#undef RISCV_ENABLE_ICSIM + /* Define if instruction compression is supported */ #undef RISCV_ENABLE_RVC |