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| author | Andrew Waterman <andrew@sifive.com> | 2018-09-12 23:56:49 -0700 |
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| committer | Andrew Waterman <andrew@sifive.com> | 2018-09-12 23:56:49 -0700 |
| commit | 6fecdb16d72b71734b35f494023f5edc8804327c (patch) | |
| tree | 0661efd7125f9fa2ab94fb66c63ced18c50b4fad /README.md | |
| parent | def4c5b104efd382e633d5fdca49508757bb5e23 (diff) | |
| download | spike-6fecdb16d72b71734b35f494023f5edc8804327c.zip spike-6fecdb16d72b71734b35f494023f5edc8804327c.tar.gz spike-6fecdb16d72b71734b35f494023f5edc8804327c.tar.bz2 | |
Update README
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 15 |
1 files changed, 6 insertions, 9 deletions
@@ -1,18 +1,15 @@ -RISC-V ISA Simulator -====================== - -Author : Andrew Waterman, Yunsup Lee - -Date : June 19, 2011 - -Version : (under version control) +Spike RISC-V ISA Simulator +============================ About ------------- -The RISC-V ISA Simulator implements a functional model of one or more +Spike, the RISC-V ISA Simulator, implements a functional model of one or more RISC-V processors. +Spike is named after the golden spike used to celebrate the completion of the +US transcontinental railway. + Build Steps --------------- |