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| author | Andrew Waterman <andrew@sifive.com> | 2019-03-30 15:09:15 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-03-30 15:09:15 -0700 |
| commit | 60743fe5c582dfe79d28493bcd1ddc34f76b0416 (patch) | |
| tree | 0c736d30d8841f776bc0f764cd0e2bc4caf5d734 | |
| parent | 9c384609b0bc0f87745a30b38e499c9a546b69f6 (diff) | |
| download | spike-60743fe5c582dfe79d28493bcd1ddc34f76b0416.zip spike-60743fe5c582dfe79d28493bcd1ddc34f76b0416.tar.gz spike-60743fe5c582dfe79d28493bcd1ddc34f76b0416.tar.bz2 | |
RV32Q is not invalid
https://github.com/riscv/riscv-isa-manual/commit/013ba6dc8a504ee4ad7bee42554fecaef7ba797f#diff-2a8fece1cbcdf623cafbce866ea7d4d0R7
| -rw-r--r-- | riscv/processor.cc | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index f8c4446..189b7db 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -113,9 +113,6 @@ void processor_t::parse_isa_string(const char* str) if (supports_extension('Q') && !supports_extension('D')) bad_isa_string(str); - if (supports_extension('Q') && max_xlen < 64) - bad_isa_string(str); - max_isa = state.misa; } |