rvv: remove legacy check 1905

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

268 files changed, 0 insertions, 274 deletions

diff --git a/riscv/decode.h b/riscv/decode.h
index 4fd5321..36dc1fe 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -357,9 +357,6 @@ inline long double to_f(float128_t f){long double r; memcpy(&r, &f, sizeof(r));
   while (0);
 #endif
 
-#define VI_CHECK_1905 \
-  while (0);
-
 extern bool g_vector_mistrap;
 
 //
diff --git a/riscv/insns/vaadd_vi.h b/riscv/insns/vaadd_vi.h
index d4fb8a3..5f8d5f5 100644
--- a/riscv/insns/vaadd_vi.h
+++ b/riscv/insns/vaadd_vi.h
@@ -7,4 +7,3 @@ VI_VI_LOOP
   result = vzext(result >> 1, sew);
   vd = result;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vaadd_vv.h b/riscv/insns/vaadd_vv.h
index f24d8cf..b479970 100644
--- a/riscv/insns/vaadd_vv.h
+++ b/riscv/insns/vaadd_vv.h
@@ -1,3 +1,2 @@
 // vaadd.vv vd, vs2, vs1
 VI_VVX_LOOP_AVG(vs1, +);
-VI_CHECK_1905
diff --git a/riscv/insns/vaadd_vx.h b/riscv/insns/vaadd_vx.h
index f41ad89..c811a0a 100644
--- a/riscv/insns/vaadd_vx.h
+++ b/riscv/insns/vaadd_vx.h
@@ -1,3 +1,2 @@
 // vaadd.vx vd, vs2, rs1
 VI_VVX_LOOP_AVG(rs1, +);
-VI_CHECK_1905
diff --git a/riscv/insns/vadc_vim.h b/riscv/insns/vadc_vim.h
index 1c0759d..e21e2f8 100644
--- a/riscv/insns/vadc_vim.h
+++ b/riscv/insns/vadc_vim.h
@@ -9,4 +9,3 @@ VI_VI_LOOP
   uint128_t res = (op_mask & simm5) + (op_mask & vs2) + carry;
   vd = res;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vadc_vvm.h b/riscv/insns/vadc_vvm.h
index 7bafdc3..b708ac1 100644
--- a/riscv/insns/vadc_vvm.h
+++ b/riscv/insns/vadc_vvm.h
@@ -9,4 +9,3 @@ VI_VV_LOOP
   uint128_t res = (op_mask & vs1) + (op_mask & vs2) + carry;
   vd = res;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vadc_vxm.h b/riscv/insns/vadc_vxm.h
index 714fce8..6c6e6dc 100644
--- a/riscv/insns/vadc_vxm.h
+++ b/riscv/insns/vadc_vxm.h
@@ -9,4 +9,3 @@ VI_VX_LOOP
   uint128_t res = (op_mask & rs1) + (op_mask & vs2) + carry;
   vd = res;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vadd_vi.h b/riscv/insns/vadd_vi.h
index bf56e52..45fc6b7 100644
--- a/riscv/insns/vadd_vi.h
+++ b/riscv/insns/vadd_vi.h
@@ -3,4 +3,3 @@ VI_VI_LOOP
 ({
   vd = simm5 + vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vadd_vv.h b/riscv/insns/vadd_vv.h
index 0016c9e..45c6bdc 100644
--- a/riscv/insns/vadd_vv.h
+++ b/riscv/insns/vadd_vv.h
@@ -3,4 +3,3 @@ VI_VV_LOOP
 ({
   vd = vs1 + vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vadd_vx.h b/riscv/insns/vadd_vx.h
index 397e802..33e72ee 100644
--- a/riscv/insns/vadd_vx.h
+++ b/riscv/insns/vadd_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP
 ({
   vd = rs1 + vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vand_vi.h b/riscv/insns/vand_vi.h
index 1bbaaf3..dd9618b 100644
--- a/riscv/insns/vand_vi.h
+++ b/riscv/insns/vand_vi.h
@@ -3,4 +3,3 @@ VI_VI_LOOP
 ({
   vd = simm5 & vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vand_vv.h b/riscv/insns/vand_vv.h
index 8a96e25..65558e4 100644
--- a/riscv/insns/vand_vv.h
+++ b/riscv/insns/vand_vv.h
@@ -3,4 +3,3 @@ VI_VV_LOOP
 ({
   vd = vs1 & vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vand_vx.h b/riscv/insns/vand_vx.h
index 1103cf5..8eea1ed 100644
--- a/riscv/insns/vand_vx.h
+++ b/riscv/insns/vand_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP
 ({
   vd = rs1 & vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vasub_vv.h b/riscv/insns/vasub_vv.h
index ab6a10f..5a5ccc9 100644
--- a/riscv/insns/vasub_vv.h
+++ b/riscv/insns/vasub_vv.h
@@ -1,3 +1,2 @@
 // vasub.vv vd, vs2, vs1
 VI_VVX_LOOP_AVG(vs1, -);
-VI_CHECK_1905
diff --git a/riscv/insns/vasub_vx.h b/riscv/insns/vasub_vx.h
index 0fa98d5..c3cad4b 100644
--- a/riscv/insns/vasub_vx.h
+++ b/riscv/insns/vasub_vx.h
@@ -1,3 +1,2 @@
 // vasub.vx vd, vs2, rs1
 VI_VVX_LOOP_AVG(rs1, -);
-VI_CHECK_1905
diff --git a/riscv/insns/vcompress_vm.h b/riscv/insns/vcompress_vm.h
index 54c093e..b056b0e 100644
--- a/riscv/insns/vcompress_vm.h
+++ b/riscv/insns/vcompress_vm.h
@@ -39,4 +39,3 @@ if (vl > 0 && TAIL_ZEROING) {
   memset(tail, 0, (P.VU.vlmax - pos) * ((sew >> 3) * 1));
 }
 
-VI_CHECK_1905
diff --git a/riscv/insns/vdiv_vv.h b/riscv/insns/vdiv_vv.h
index 7eb7dc5..67da162 100644
--- a/riscv/insns/vdiv_vv.h
+++ b/riscv/insns/vdiv_vv.h
@@ -8,4 +8,3 @@ VI_VV_LOOP
   else
     vd = vs2 / vs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vdiv_vx.h b/riscv/insns/vdiv_vx.h
index 6a89678..1a152bd 100644
--- a/riscv/insns/vdiv_vx.h
+++ b/riscv/insns/vdiv_vx.h
@@ -8,4 +8,3 @@ VI_VX_LOOP
   else
     vd = vs2 / rs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vdivu_vv.h b/riscv/insns/vdivu_vv.h
index 3098a48..ef6e777 100644
--- a/riscv/insns/vdivu_vv.h
+++ b/riscv/insns/vdivu_vv.h
@@ -6,4 +6,3 @@ VI_VV_ULOOP
   else
     vd = vs2 / vs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vdivu_vx.h b/riscv/insns/vdivu_vx.h
index ef07124..7ffe1c6 100644
--- a/riscv/insns/vdivu_vx.h
+++ b/riscv/insns/vdivu_vx.h
@@ -6,4 +6,3 @@ VI_VX_ULOOP
   else
     vd = vs2 / rs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vdot_vv.h b/riscv/insns/vdot_vv.h
index d0403b1..7685230 100644
--- a/riscv/insns/vdot_vv.h
+++ b/riscv/insns/vdot_vv.h
@@ -3,4 +3,3 @@ VI_VV_LOOP
 ({
   vd += vs2 * vs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vdotu_vv.h b/riscv/insns/vdotu_vv.h
index c2cdcc9..9c4c59d 100644
--- a/riscv/insns/vdotu_vv.h
+++ b/riscv/insns/vdotu_vv.h
@@ -3,4 +3,3 @@ VI_VV_ULOOP
 ({
   vd += vs2 * vs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfcvt_f_x_v.h b/riscv/insns/vfcvt_f_x_v.h
index 29ace9e..311f875 100644
--- a/riscv/insns/vfcvt_f_x_v.h
+++ b/riscv/insns/vfcvt_f_x_v.h
@@ -4,4 +4,3 @@ VI_VFP_VV_LOOP
   auto vs2_i = P.VU.elt<int32_t>(rs2_num, i);
   vd = i32_to_f32(vs2_i);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfcvt_f_xu_v.h b/riscv/insns/vfcvt_f_xu_v.h
index 73443ad..ceabea3 100644
--- a/riscv/insns/vfcvt_f_xu_v.h
+++ b/riscv/insns/vfcvt_f_xu_v.h
@@ -4,4 +4,3 @@ VI_VFP_VV_LOOP
   auto vs2_u = P.VU.elt<uint32_t>(rs2_num, i);
   vd = ui32_to_f32(vs2_u);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfcvt_x_f_v.h b/riscv/insns/vfcvt_x_f_v.h
index d2b1067..ee53c6d 100644
--- a/riscv/insns/vfcvt_x_f_v.h
+++ b/riscv/insns/vfcvt_x_f_v.h
@@ -3,4 +3,3 @@ VI_VFP_VV_LOOP
 ({
   P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, STATE.frm, true);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfcvt_xu_f_v.h b/riscv/insns/vfcvt_xu_f_v.h
index 9fa813b..76c7735 100644
--- a/riscv/insns/vfcvt_xu_f_v.h
+++ b/riscv/insns/vfcvt_xu_f_v.h
@@ -3,4 +3,3 @@ VI_VFP_VV_LOOP
 ({
   P.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, STATE.frm, true);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfdot_vv.h b/riscv/insns/vfdot_vv.h
index ea93bdf..11c8bce 100644
--- a/riscv/insns/vfdot_vv.h
+++ b/riscv/insns/vfdot_vv.h
@@ -3,4 +3,3 @@ VI_VFP_VV_LOOP
 ({
   vd = f32_add(vd, f32_mul(vs2, vs1));
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfirst_m.h b/riscv/insns/vfirst_m.h
index fa000ec..40e2f09 100644
--- a/riscv/insns/vfirst_m.h
+++ b/riscv/insns/vfirst_m.h
@@ -18,4 +18,3 @@ for (reg_t i=P.VU.vstart; i < vl; ++i) {
 }
 P.VU.vstart = 0;
 WRITE_RD(pos);
-VI_CHECK_1905
diff --git a/riscv/insns/vfncvt_f_f_v.h b/riscv/insns/vfncvt_f_f_v.h
index 1502f1e..b35cd60 100644
--- a/riscv/insns/vfncvt_f_f_v.h
+++ b/riscv/insns/vfncvt_f_f_v.h
@@ -4,4 +4,3 @@ VI_VFP_LOOP_BASE
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i) = f64_to_f32(vs2);
 VI_VFP_LOOP_END
-VI_CHECK_1905
diff --git a/riscv/insns/vfncvt_f_x_v.h b/riscv/insns/vfncvt_f_x_v.h
index b6f3c3f..69bdba8 100644
--- a/riscv/insns/vfncvt_f_x_v.h
+++ b/riscv/insns/vfncvt_f_x_v.h
@@ -4,4 +4,3 @@ VI_VFP_LOOP_BASE
   auto vs2 = P.VU.elt<int64_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i) = i64_to_f32(vs2);
 VI_VFP_LOOP_END
-VI_CHECK_1905
diff --git a/riscv/insns/vfncvt_f_xu_v.h b/riscv/insns/vfncvt_f_xu_v.h
index 6d38324..6f37734 100644
--- a/riscv/insns/vfncvt_f_xu_v.h
+++ b/riscv/insns/vfncvt_f_xu_v.h
@@ -4,4 +4,3 @@ VI_VFP_LOOP_BASE
   auto vs2 = P.VU.elt<uint64_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i) = ui64_to_f32(vs2);
 VI_VFP_LOOP_END
-VI_CHECK_1905
diff --git a/riscv/insns/vfncvt_x_f_v.h b/riscv/insns/vfncvt_x_f_v.h
index 57dab3c..8985f1b 100644
--- a/riscv/insns/vfncvt_x_f_v.h
+++ b/riscv/insns/vfncvt_x_f_v.h
@@ -4,4 +4,3 @@ VI_VFP_LOOP_BASE
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<int32_t>(rd_num, i) = f64_to_i32(vs2, STATE.frm, true);
 VI_VFP_LOOP_END
-VI_CHECK_1905
diff --git a/riscv/insns/vfncvt_xu_f_v.h b/riscv/insns/vfncvt_xu_f_v.h
index f041e90..2db8d82 100644
--- a/riscv/insns/vfncvt_xu_f_v.h
+++ b/riscv/insns/vfncvt_xu_f_v.h
@@ -4,4 +4,3 @@ VI_VFP_LOOP_BASE
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<uint32_t>(rd_num, i) = f64_to_ui32(vs2, STATE.frm, true);
 VI_VFP_LOOP_END
-VI_CHECK_1905
diff --git a/riscv/insns/vfredmax_vs.h b/riscv/insns/vfredmax_vs.h
index 4f1dde2..dca10bf 100644
--- a/riscv/insns/vfredmax_vs.h
+++ b/riscv/insns/vfredmax_vs.h
@@ -3,4 +3,3 @@ VI_VFP_VV_LOOP_REDUCTION
 ({
   vd_0 = f32_max(vd_0, vs2);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfredmin_vs.h b/riscv/insns/vfredmin_vs.h
index 4f77d3c..b4556bc 100644
--- a/riscv/insns/vfredmin_vs.h
+++ b/riscv/insns/vfredmin_vs.h
@@ -3,4 +3,3 @@ VI_VFP_VV_LOOP_REDUCTION
 ({
   vd_0 = f32_min(vd_0, vs2);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfredosum_vs.h b/riscv/insns/vfredosum_vs.h
index e68b8d5..87422ee 100644
--- a/riscv/insns/vfredosum_vs.h
+++ b/riscv/insns/vfredosum_vs.h
@@ -3,4 +3,3 @@ VI_VFP_VV_LOOP_REDUCTION
 ({
   vd_0 = f32_add(vd_0, vs2);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfredsum_vs.h b/riscv/insns/vfredsum_vs.h
index 17e42f3..b50b45f 100644
--- a/riscv/insns/vfredsum_vs.h
+++ b/riscv/insns/vfredsum_vs.h
@@ -3,4 +3,3 @@ VI_VFP_VV_LOOP_REDUCTION
 ({
   vd_0 = f32_add(vd_0, vs2);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfwadd_vf.h b/riscv/insns/vfwadd_vf.h
index 59a683c..ecac202 100644
--- a/riscv/insns/vfwadd_vf.h
+++ b/riscv/insns/vfwadd_vf.h
@@ -3,4 +3,3 @@ VI_VFP_VF_LOOP_WIDE
 ({
   vd = f64_add(vs2, rs1);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfwadd_vv.h b/riscv/insns/vfwadd_vv.h
index 3827f85..0665cdc 100644
--- a/riscv/insns/vfwadd_vv.h
+++ b/riscv/insns/vfwadd_vv.h
@@ -3,4 +3,3 @@ VI_VFP_VV_LOOP_WIDE
 ({
   vd = f64_add(vs2, vs1);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfwadd_wf.h b/riscv/insns/vfwadd_wf.h
index 54bc92e..eb38d0d 100644
--- a/riscv/insns/vfwadd_wf.h
+++ b/riscv/insns/vfwadd_wf.h
@@ -3,4 +3,3 @@ VI_VFP_WF_LOOP_WIDE
 ({
   vd = f64_add(vs2, rs1);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfwadd_wv.h b/riscv/insns/vfwadd_wv.h
index 2f77866..675ef22 100644
--- a/riscv/insns/vfwadd_wv.h
+++ b/riscv/insns/vfwadd_wv.h
@@ -3,4 +3,3 @@ VI_VFP_WV_LOOP_WIDE
 ({
   vd = f64_add(vs2, vs1);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfwcvt_f_f_v.h b/riscv/insns/vfwcvt_f_f_v.h
index 761adc4..4d6b4fc 100644
--- a/riscv/insns/vfwcvt_f_f_v.h
+++ b/riscv/insns/vfwcvt_f_f_v.h
@@ -5,4 +5,3 @@ VI_VFP_LOOP_BASE
   P.VU.elt<float64_t>(rd_num, i) = f32_to_f64(vs2);
   set_fp_exceptions;
 VI_VFP_LOOP_WIDE_END
-VI_CHECK_1905
diff --git a/riscv/insns/vfwcvt_f_x_v.h b/riscv/insns/vfwcvt_f_x_v.h
index 37e76a3..ab5d825 100644
--- a/riscv/insns/vfwcvt_f_x_v.h
+++ b/riscv/insns/vfwcvt_f_x_v.h
@@ -5,4 +5,3 @@ VI_VFP_LOOP_BASE
   P.VU.elt<float64_t>(rd_num, i) = i32_to_f64(vs2);
   set_fp_exceptions;
 VI_VFP_LOOP_WIDE_END
-VI_CHECK_1905
diff --git a/riscv/insns/vfwcvt_f_xu_v.h b/riscv/insns/vfwcvt_f_xu_v.h
index 3bba46e..8af8d7c 100644
--- a/riscv/insns/vfwcvt_f_xu_v.h
+++ b/riscv/insns/vfwcvt_f_xu_v.h
@@ -5,4 +5,3 @@ VI_VFP_LOOP_BASE
   P.VU.elt<float64_t>(rd_num, i) = ui32_to_f64(vs2);
   set_fp_exceptions;
 VI_VFP_LOOP_WIDE_END
-VI_CHECK_1905
diff --git a/riscv/insns/vfwcvt_x_f_v.h b/riscv/insns/vfwcvt_x_f_v.h
index 6e78dc9..06e81d4 100644
--- a/riscv/insns/vfwcvt_x_f_v.h
+++ b/riscv/insns/vfwcvt_x_f_v.h
@@ -5,4 +5,3 @@ VI_VFP_LOOP_BASE
   P.VU.elt<int64_t>(rd_num, i) = f32_to_i64(vs2, STATE.frm, true);
   set_fp_exceptions;
 VI_VFP_LOOP_WIDE_END
-VI_CHECK_1905
diff --git a/riscv/insns/vfwcvt_xu_f_v.h b/riscv/insns/vfwcvt_xu_f_v.h
index eb39768..cc82481 100644
--- a/riscv/insns/vfwcvt_xu_f_v.h
+++ b/riscv/insns/vfwcvt_xu_f_v.h
@@ -5,4 +5,3 @@ VI_VFP_LOOP_BASE
   P.VU.elt<uint64_t>(rd_num, i) = f32_to_ui64(vs2, STATE.frm, true);
   set_fp_exceptions;
 VI_VFP_LOOP_WIDE_END
-VI_CHECK_1905
diff --git a/riscv/insns/vfwmacc_vf.h b/riscv/insns/vfwmacc_vf.h
index adc0e02..6ee011e 100644
--- a/riscv/insns/vfwmacc_vf.h
+++ b/riscv/insns/vfwmacc_vf.h
@@ -3,4 +3,3 @@ VI_VFP_VF_LOOP_WIDE
 ({
   vd = f64_mulAdd(rs1, vs2, vd);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfwmacc_vv.h b/riscv/insns/vfwmacc_vv.h
index d7a5d1a..99839af 100644
--- a/riscv/insns/vfwmacc_vv.h
+++ b/riscv/insns/vfwmacc_vv.h
@@ -3,4 +3,3 @@ VI_VFP_VV_LOOP_WIDE
 ({
   vd = f64_mulAdd(vs1, vs2, vd);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfwmsac_vf.h b/riscv/insns/vfwmsac_vf.h
index df4b379..ea8f050 100644
--- a/riscv/insns/vfwmsac_vf.h
+++ b/riscv/insns/vfwmsac_vf.h
@@ -3,4 +3,3 @@ VI_VFP_VF_LOOP_WIDE
 ({
   vd = f64_mulAdd(rs1, vs2, f64(vd.v ^ F64_SIGN));
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfwmsac_vv.h b/riscv/insns/vfwmsac_vv.h
index 6471c75..8157170 100644
--- a/riscv/insns/vfwmsac_vv.h
+++ b/riscv/insns/vfwmsac_vv.h
@@ -3,4 +3,3 @@ VI_VFP_VV_LOOP_WIDE
 ({
   vd = f64_mulAdd(vs1, vs2, f64(vd.v ^ F64_SIGN));
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfwmul_vf.h b/riscv/insns/vfwmul_vf.h
index 6b97086..884e66f 100644
--- a/riscv/insns/vfwmul_vf.h
+++ b/riscv/insns/vfwmul_vf.h
@@ -3,4 +3,3 @@ VI_VFP_VF_LOOP_WIDE
 ({
   vd = f64_mul(vs2, rs1);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfwmul_vv.h b/riscv/insns/vfwmul_vv.h
index a7ca199..f8e717e 100644
--- a/riscv/insns/vfwmul_vv.h
+++ b/riscv/insns/vfwmul_vv.h
@@ -3,4 +3,3 @@ VI_VFP_VV_LOOP_WIDE
 ({
   vd = f64_mul(vs2, vs1);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfwnmacc_vf.h b/riscv/insns/vfwnmacc_vf.h
index 95352db..bccc24f 100644
--- a/riscv/insns/vfwnmacc_vf.h
+++ b/riscv/insns/vfwnmacc_vf.h
@@ -3,4 +3,3 @@ VI_VFP_VF_LOOP_WIDE
 ({
   vd = f64_mulAdd(f64(rs1.v ^ F64_SIGN), vs2, f64(vd.v ^ F64_SIGN));
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfwnmacc_vv.h b/riscv/insns/vfwnmacc_vv.h
index 8fa34a8..3dcba1d 100644
--- a/riscv/insns/vfwnmacc_vv.h
+++ b/riscv/insns/vfwnmacc_vv.h
@@ -3,4 +3,3 @@ VI_VFP_VV_LOOP_WIDE
 ({
   vd = f64_mulAdd(f64(vs1.v ^ F64_SIGN), vs2, f64(vd.v ^ F64_SIGN));
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfwnmsac_vf.h b/riscv/insns/vfwnmsac_vf.h
index a235427..32ef624 100644
--- a/riscv/insns/vfwnmsac_vf.h
+++ b/riscv/insns/vfwnmsac_vf.h
@@ -3,4 +3,3 @@ VI_VFP_VF_LOOP_WIDE
 ({
   vd = f64_mulAdd(f64(rs1.v ^ F64_SIGN), vs2, vd);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfwnmsac_vv.h b/riscv/insns/vfwnmsac_vv.h
index 5dcb6c0..d2447e1 100644
--- a/riscv/insns/vfwnmsac_vv.h
+++ b/riscv/insns/vfwnmsac_vv.h
@@ -3,4 +3,3 @@ VI_VFP_VV_LOOP_WIDE
 ({
   vd = f64_mulAdd(f64(vs1.v ^ F64_SIGN), vs2, vd);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfwredosum_vs.h b/riscv/insns/vfwredosum_vs.h
index 1ec4201..b47e2c7 100644
--- a/riscv/insns/vfwredosum_vs.h
+++ b/riscv/insns/vfwredosum_vs.h
@@ -3,4 +3,3 @@ VI_VFP_VV_LOOP_WIDE_REDUCTION
 ({
   vd_0 = f64_add(vd_0, vs2);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfwredsum_vs.h b/riscv/insns/vfwredsum_vs.h
index e42a94f..3ce591b 100644
--- a/riscv/insns/vfwredsum_vs.h
+++ b/riscv/insns/vfwredsum_vs.h
@@ -3,4 +3,3 @@ VI_VFP_VV_LOOP_WIDE_REDUCTION
 ({
   vd_0 = f64_add(vd_0, vs2);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfwsub_vf.h b/riscv/insns/vfwsub_vf.h
index 6a5a471..1d20c38 100644
--- a/riscv/insns/vfwsub_vf.h
+++ b/riscv/insns/vfwsub_vf.h
@@ -3,4 +3,3 @@ VI_VFP_VF_LOOP_WIDE
 ({
   vd = f64_sub(vs2, rs1);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfwsub_vv.h b/riscv/insns/vfwsub_vv.h
index 668511c..0a72fea 100644
--- a/riscv/insns/vfwsub_vv.h
+++ b/riscv/insns/vfwsub_vv.h
@@ -3,4 +3,3 @@ VI_VFP_VV_LOOP_WIDE
 ({
   vd = f64_sub(vs2, vs1);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfwsub_wf.h b/riscv/insns/vfwsub_wf.h
index d996a79..fa3d747 100644
--- a/riscv/insns/vfwsub_wf.h
+++ b/riscv/insns/vfwsub_wf.h
@@ -3,4 +3,3 @@ VI_VFP_WF_LOOP_WIDE
 ({
   vd = f64_sub(vs2, rs1);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vfwsub_wv.h b/riscv/insns/vfwsub_wv.h
index 6314c28..4c6fcf6 100644
--- a/riscv/insns/vfwsub_wv.h
+++ b/riscv/insns/vfwsub_wv.h
@@ -3,4 +3,3 @@ VI_VFP_WV_LOOP_WIDE
 ({
   vd = f64_sub(vs2, vs1);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vid_v.h b/riscv/insns/vid_v.h
index fe5ceae..df6dd04 100644
--- a/riscv/insns/vid_v.h
+++ b/riscv/insns/vid_v.h
@@ -28,4 +28,3 @@ for (reg_t i = P.VU.vstart ; i < P.VU.vl; ++i) {
 
 VI_TAIL_ZERO(1);
 P.VU.vstart = 0;
-VI_CHECK_1905
diff --git a/riscv/insns/viota_m.h b/riscv/insns/viota_m.h
index 60d65e2..fde0291 100644
--- a/riscv/insns/viota_m.h
+++ b/riscv/insns/viota_m.h
@@ -50,4 +50,3 @@ for (reg_t i = 0; i < vl; ++i) {
 }
 
 VI_TAIL_ZERO(1);
-VI_CHECK_1905
diff --git a/riscv/insns/vlb_v.h b/riscv/insns/vlb_v.h
index 7d98d07..a83587d 100644
--- a/riscv/insns/vlb_v.h
+++ b/riscv/insns/vlb_v.h
@@ -1,4 +1,3 @@
 // vlb.v and vlseg[2-8]b.v
 require(P.VU.vsew >= e8);
 VI_LD(0, i * nf + fn, int8, 1);
-VI_CHECK_1905
diff --git a/riscv/insns/vlbff_v.h b/riscv/insns/vlbff_v.h
index 605cf83..6517315 100644
--- a/riscv/insns/vlbff_v.h
+++ b/riscv/insns/vlbff_v.h
@@ -1,3 +1,2 @@
 // vlbff.v and vlseg[2-8]bff.v
 VI_LDST_FF(int, 8);
-VI_CHECK_1905
diff --git a/riscv/insns/vlbu_v.h b/riscv/insns/vlbu_v.h
index 17954ec..c1e3ea7 100644
--- a/riscv/insns/vlbu_v.h
+++ b/riscv/insns/vlbu_v.h
@@ -1,4 +1,3 @@
 // vlbu.v and vlseg[2-8]bu.v
 require(P.VU.vsew >= e8);
 VI_LD(0, i * nf + fn, uint8, 1);
-VI_CHECK_1905
diff --git a/riscv/insns/vlbuff_v.h b/riscv/insns/vlbuff_v.h
index 1319c38..53a0685 100644
--- a/riscv/insns/vlbuff_v.h
+++ b/riscv/insns/vlbuff_v.h
@@ -1,3 +1,2 @@
 // vlbuff.v and vlseg[2-8]buff.v
 VI_LDST_FF(uint, 8);
-VI_CHECK_1905
diff --git a/riscv/insns/vle_v.h b/riscv/insns/vle_v.h
index 3a4ddc9..67261cc 100644
--- a/riscv/insns/vle_v.h
+++ b/riscv/insns/vle_v.h
@@ -11,4 +11,3 @@ if (sew == e8) {
   VI_LD(0, (i * nf + fn), int64, 8);
 }
 
-VI_CHECK_1905
diff --git a/riscv/insns/vleff_v.h b/riscv/insns/vleff_v.h
index ed8e103..59869a3 100644
--- a/riscv/insns/vleff_v.h
+++ b/riscv/insns/vleff_v.h
@@ -53,4 +53,3 @@ for (reg_t i = 0; i < P.VU.vlmax && vl != 0; ++i) {
 }
 
 P.VU.vstart = 0;
-VI_CHECK_1905
diff --git a/riscv/insns/vlh_v.h b/riscv/insns/vlh_v.h
index d343e61..d976693 100644
--- a/riscv/insns/vlh_v.h
+++ b/riscv/insns/vlh_v.h
@@ -1,4 +1,3 @@
 // vlh.v and vlseg[2-8]h.v
 require(P.VU.vsew >= e16);
 VI_LD(0, i * nf + fn, int16, 2);
-VI_CHECK_1905
diff --git a/riscv/insns/vlhff_v.h b/riscv/insns/vlhff_v.h
index c612c8c..c4c2d8e 100644
--- a/riscv/insns/vlhff_v.h
+++ b/riscv/insns/vlhff_v.h
@@ -1,3 +1,2 @@
 // vlh.v and vlseg[2-8]hff.v
 VI_LDST_FF(int, 16);
-VI_CHECK_1905
diff --git a/riscv/insns/vlhu_v.h b/riscv/insns/vlhu_v.h
index c06113e..5b936dd 100644
--- a/riscv/insns/vlhu_v.h
+++ b/riscv/insns/vlhu_v.h
@@ -1,4 +1,3 @@
 // vlhu.v and vlseg[2-8]hu.v
 require(P.VU.vsew >= e16);
 VI_LD(0, i * nf + fn, uint16, 2);
-VI_CHECK_1905
diff --git a/riscv/insns/vlhuff_v.h b/riscv/insns/vlhuff_v.h
index cfa02f4..f23f82d 100644
--- a/riscv/insns/vlhuff_v.h
+++ b/riscv/insns/vlhuff_v.h
@@ -1,3 +1,2 @@
 // vlhuff.v and vlseg[2-8]huff.v
 VI_LDST_FF(uint, 16);
-VI_CHECK_1905
diff --git a/riscv/insns/vlsb_v.h b/riscv/insns/vlsb_v.h
index 78c087d..fd57bbe 100644
--- a/riscv/insns/vlsb_v.h
+++ b/riscv/insns/vlsb_v.h
@@ -1,4 +1,3 @@
 // vlsb.v and vlsseg[2-8]b.v
 require(P.VU.vsew >= e8);
 VI_LD(i * RS2, fn, int8, 1);
-VI_CHECK_1905
diff --git a/riscv/insns/vlsbu_v.h b/riscv/insns/vlsbu_v.h
index 1476be9..4376833 100644
--- a/riscv/insns/vlsbu_v.h
+++ b/riscv/insns/vlsbu_v.h
@@ -1,4 +1,3 @@
 // vlsb.v and vlsseg[2-8]b.v
 require(P.VU.vsew >= e8);
 VI_LD(i * RS2, fn, uint8, 1);
-VI_CHECK_1905
diff --git a/riscv/insns/vlse_v.h b/riscv/insns/vlse_v.h
index 940431e..2ac2f29 100644
--- a/riscv/insns/vlse_v.h
+++ b/riscv/insns/vlse_v.h
@@ -11,4 +11,3 @@ if (sew == e8) {
   VI_LD(i * RS2, fn, int64, 8);
 }
 
-VI_CHECK_1905
diff --git a/riscv/insns/vlsh_v.h b/riscv/insns/vlsh_v.h
index d13eefb..2834353 100644
--- a/riscv/insns/vlsh_v.h
+++ b/riscv/insns/vlsh_v.h
@@ -1,4 +1,3 @@
 // vlsh.v and vlsseg[2-8]h.v
 require(P.VU.vsew >= e16);
 VI_LD(i * RS2, fn, int16, 2);
-VI_CHECK_1905
diff --git a/riscv/insns/vlshu_v.h b/riscv/insns/vlshu_v.h
index 6d78bbc..9b11b66 100644
--- a/riscv/insns/vlshu_v.h
+++ b/riscv/insns/vlshu_v.h
@@ -1,4 +1,3 @@
 // vlsh.v and vlsseg[2-8]h.v
 require(P.VU.vsew >= e16);
 VI_LD(i * RS2, fn, uint16, 2);
-VI_CHECK_1905
diff --git a/riscv/insns/vlsw_v.h b/riscv/insns/vlsw_v.h
index 44ba764..6681acb 100644
--- a/riscv/insns/vlsw_v.h
+++ b/riscv/insns/vlsw_v.h
@@ -1,4 +1,3 @@
 // vlsw.v and vlsseg[2-8]w.v
 require(P.VU.vsew >= e32);
 VI_LD(i * RS2, fn, int32, 4);
-VI_CHECK_1905
diff --git a/riscv/insns/vlswu_v.h b/riscv/insns/vlswu_v.h
index 6a50030..865af22 100644
--- a/riscv/insns/vlswu_v.h
+++ b/riscv/insns/vlswu_v.h
@@ -1,4 +1,3 @@
 // vlsw.v and vlsseg[2-8]w.v
 require(P.VU.vsew >= e32);
 VI_LD(i * RS2, fn, uint32, 4);
-VI_CHECK_1905
diff --git a/riscv/insns/vlw_v.h b/riscv/insns/vlw_v.h
index 2241c32..b62f3d0 100644
--- a/riscv/insns/vlw_v.h
+++ b/riscv/insns/vlw_v.h
@@ -1,6 +1,3 @@
 // vlw.v and vlseg[2-8]w.v
 require(P.VU.vsew >= e32);
 VI_LD(0, i * nf + fn, int32, 4);
-if (nf >= 2) {
-  VI_CHECK_1905;
-}
diff --git a/riscv/insns/vlwff_v.h b/riscv/insns/vlwff_v.h
index 67df956..b671b01 100644
--- a/riscv/insns/vlwff_v.h
+++ b/riscv/insns/vlwff_v.h
@@ -1,4 +1,3 @@
 // vlwff.v
 // vlw.v and vlseg[2-8]wff.v
 VI_LDST_FF(int, 32);
-VI_CHECK_1905
diff --git a/riscv/insns/vlwu_v.h b/riscv/insns/vlwu_v.h
index 6b75a46..0db711f 100644
--- a/riscv/insns/vlwu_v.h
+++ b/riscv/insns/vlwu_v.h
@@ -2,5 +2,4 @@
 require(P.VU.vsew >= e32);
 VI_LD(0, i * nf + fn, uint32, 4);
 if (nf >= 2) {
-  VI_CHECK_1905;
 }
diff --git a/riscv/insns/vlwuff_v.h b/riscv/insns/vlwuff_v.h
index d095384..d50cb69 100644
--- a/riscv/insns/vlwuff_v.h
+++ b/riscv/insns/vlwuff_v.h
@@ -1,3 +1,2 @@
 // vlwuff.v and vlseg[2-8]wuff.v
 VI_LDST_FF(uint, 32);
-VI_CHECK_1905
diff --git a/riscv/insns/vlxb_v.h b/riscv/insns/vlxb_v.h
index a553dfe..5a99bd3 100644
--- a/riscv/insns/vlxb_v.h
+++ b/riscv/insns/vlxb_v.h
@@ -2,4 +2,3 @@
 require(P.VU.vsew >= e8);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
 VI_LD(index[i], fn, int8, 1);
-VI_CHECK_1905
diff --git a/riscv/insns/vlxbu_v.h b/riscv/insns/vlxbu_v.h
index 7c1c3f6..daf2d2b 100644
--- a/riscv/insns/vlxbu_v.h
+++ b/riscv/insns/vlxbu_v.h
@@ -2,4 +2,3 @@
 require(P.VU.vsew >= e8);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
 VI_LD(index[i], fn, uint8, 1);
-VI_CHECK_1905
diff --git a/riscv/insns/vlxe_v.h b/riscv/insns/vlxe_v.h
index f9a05c4..b1190a8 100644
--- a/riscv/insns/vlxe_v.h
+++ b/riscv/insns/vlxe_v.h
@@ -11,4 +11,3 @@ if (sew == e8) {
   VI_LD(index[i], fn, int64, 8);
 }
 
-VI_CHECK_1905
diff --git a/riscv/insns/vlxh_v.h b/riscv/insns/vlxh_v.h
index 410a7b0..98145db 100644
--- a/riscv/insns/vlxh_v.h
+++ b/riscv/insns/vlxh_v.h
@@ -2,4 +2,3 @@
 require(P.VU.vsew >= e16);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
 VI_LD(index[i], fn, int16, 2);
-VI_CHECK_1905
diff --git a/riscv/insns/vlxhu_v.h b/riscv/insns/vlxhu_v.h
index 8b97190..27d549c 100644
--- a/riscv/insns/vlxhu_v.h
+++ b/riscv/insns/vlxhu_v.h
@@ -2,4 +2,3 @@
 require(P.VU.vsew >= e16);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
 VI_LD(index[i], fn, uint16, 2);
-VI_CHECK_1905
diff --git a/riscv/insns/vlxw_v.h b/riscv/insns/vlxw_v.h
index e53ba7a..83300f0 100644
--- a/riscv/insns/vlxw_v.h
+++ b/riscv/insns/vlxw_v.h
@@ -2,5 +2,4 @@
 require(P.VU.vsew >= e32);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
 VI_LD(index[i], fn, int32, 4);
-VI_CHECK_1905
 
diff --git a/riscv/insns/vlxwu_v.h b/riscv/insns/vlxwu_v.h
index 05be009..a2f9913 100644
--- a/riscv/insns/vlxwu_v.h
+++ b/riscv/insns/vlxwu_v.h
@@ -2,4 +2,3 @@
 require(P.VU.vsew >= e32);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
 VI_LD(index[i], fn, uint32, 4);
-VI_CHECK_1905
diff --git a/riscv/insns/vmacc_vv.h b/riscv/insns/vmacc_vv.h
index ee33611..e6ec93f 100644
--- a/riscv/insns/vmacc_vv.h
+++ b/riscv/insns/vmacc_vv.h
@@ -3,4 +3,3 @@ VI_VV_LOOP
 ({
   vd = vs1 * vs2 + vd;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmacc_vx.h b/riscv/insns/vmacc_vx.h
index b2bfffb..d40b264 100644
--- a/riscv/insns/vmacc_vx.h
+++ b/riscv/insns/vmacc_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP
 ({
   vd = rs1 * vs2 + vd;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmadc_vim.h b/riscv/insns/vmadc_vim.h
index 6eb8a9d..fd79089 100644
--- a/riscv/insns/vmadc_vim.h
+++ b/riscv/insns/vmadc_vim.h
@@ -12,4 +12,3 @@ VI_XI_LOOP_CARRY
   carry = (res >> sew) & 0x1u;
   vd = (vd & ~mmask) | ((carry << mpos) & mmask);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmadc_vvm.h b/riscv/insns/vmadc_vvm.h
index fb8a0a9..82042ca 100644
--- a/riscv/insns/vmadc_vvm.h
+++ b/riscv/insns/vmadc_vvm.h
@@ -12,4 +12,3 @@ VI_VV_LOOP_CARRY
   carry = (res >> sew) & 0x1u;
   vd = (vd & ~mmask) | ((carry << mpos) & mmask);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmadc_vxm.h b/riscv/insns/vmadc_vxm.h
index 80e31dd..8f26584 100644
--- a/riscv/insns/vmadc_vxm.h
+++ b/riscv/insns/vmadc_vxm.h
@@ -12,4 +12,3 @@ VI_XI_LOOP_CARRY
   carry = (res >> sew) & 0x1u;
   vd = (vd & ~mmask) | ((carry << mpos) & mmask);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmadd_vv.h b/riscv/insns/vmadd_vv.h
index 94c909c..a1c0d2e 100644
--- a/riscv/insns/vmadd_vv.h
+++ b/riscv/insns/vmadd_vv.h
@@ -3,4 +3,3 @@ VI_VV_LOOP
 ({
   vd = vd * vs1 + vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmadd_vx.h b/riscv/insns/vmadd_vx.h
index 08f3b6c..1a8a001 100644
--- a/riscv/insns/vmadd_vx.h
+++ b/riscv/insns/vmadd_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP
 ({
   vd = vd * rs1 + vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmax_vv.h b/riscv/insns/vmax_vv.h
index ef3cadc..b9f15c5 100644
--- a/riscv/insns/vmax_vv.h
+++ b/riscv/insns/vmax_vv.h
@@ -8,4 +8,3 @@ VI_VV_LOOP
   }
 
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmax_vx.h b/riscv/insns/vmax_vx.h
index bec4a4f..06f3f43 100644
--- a/riscv/insns/vmax_vx.h
+++ b/riscv/insns/vmax_vx.h
@@ -8,4 +8,3 @@ VI_VX_LOOP
   }
 
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmaxu_vv.h b/riscv/insns/vmaxu_vv.h
index 996316f..4e6868d 100644
--- a/riscv/insns/vmaxu_vv.h
+++ b/riscv/insns/vmaxu_vv.h
@@ -7,4 +7,3 @@ VI_VV_ULOOP
     vd = vs2;
   }
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmaxu_vx.h b/riscv/insns/vmaxu_vx.h
index f50a0b1..cab8918 100644
--- a/riscv/insns/vmaxu_vx.h
+++ b/riscv/insns/vmaxu_vx.h
@@ -7,4 +7,3 @@ VI_VX_ULOOP
     vd = vs2;
   }
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmin_vv.h b/riscv/insns/vmin_vv.h
index 501cc50..21da0b3 100644
--- a/riscv/insns/vmin_vv.h
+++ b/riscv/insns/vmin_vv.h
@@ -9,4 +9,3 @@ VI_VV_LOOP
 
 
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmin_vx.h b/riscv/insns/vmin_vx.h
index dd0c560..3291776 100644
--- a/riscv/insns/vmin_vx.h
+++ b/riscv/insns/vmin_vx.h
@@ -9,4 +9,3 @@ VI_VX_LOOP
 
 
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vminu_vv.h b/riscv/insns/vminu_vv.h
index a3d9897..c0ab195 100644
--- a/riscv/insns/vminu_vv.h
+++ b/riscv/insns/vminu_vv.h
@@ -7,4 +7,3 @@ VI_VV_ULOOP
     vd = vs2;
   }
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vminu_vx.h b/riscv/insns/vminu_vx.h
index 557cc5a..1055895 100644
--- a/riscv/insns/vminu_vx.h
+++ b/riscv/insns/vminu_vx.h
@@ -8,4 +8,3 @@ VI_VX_ULOOP
   }
 
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmsbc_vvm.h b/riscv/insns/vmsbc_vvm.h
index 27f8d24..3804ba8 100644
--- a/riscv/insns/vmsbc_vvm.h
+++ b/riscv/insns/vmsbc_vvm.h
@@ -12,4 +12,3 @@ VI_VV_LOOP_CARRY
   carry = (res >> sew) & 0x1u;
   vd = (vd & ~mmask) | ((carry << mpos) & mmask);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmsbc_vxm.h b/riscv/insns/vmsbc_vxm.h
index 1d0a637..d5332f5 100644
--- a/riscv/insns/vmsbc_vxm.h
+++ b/riscv/insns/vmsbc_vxm.h
@@ -12,4 +12,3 @@ VI_XI_LOOP_CARRY
   carry = (res >> sew) & 0x1u;
   vd = (vd & ~mmask) | ((carry << mpos) & mmask);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmsbf_m.h b/riscv/insns/vmsbf_m.h
index 6542ca3..3047cca 100644
--- a/riscv/insns/vmsbf_m.h
+++ b/riscv/insns/vmsbf_m.h
@@ -32,4 +32,3 @@ for (reg_t i = P.VU.vstart; i < vl; ++i) {
 
 VI_TAIL_ZERO_MASK(rd_num);
 P.VU.vstart = 0;
-VI_CHECK_1905
diff --git a/riscv/insns/vmseq_vi.h b/riscv/insns/vmseq_vi.h
index a348ae8..cfc1682 100644
--- a/riscv/insns/vmseq_vi.h
+++ b/riscv/insns/vmseq_vi.h
@@ -3,4 +3,3 @@ VI_VI_LOOP_CMP
 ({
   res = simm5 == vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmseq_vv.h b/riscv/insns/vmseq_vv.h
index 5856d96..91fd204 100644
--- a/riscv/insns/vmseq_vv.h
+++ b/riscv/insns/vmseq_vv.h
@@ -4,4 +4,3 @@ VI_VV_LOOP_CMP
   res = vs2 == vs1;
 })
 
-VI_CHECK_1905
diff --git a/riscv/insns/vmseq_vx.h b/riscv/insns/vmseq_vx.h
index 951d9c8..ab63323 100644
--- a/riscv/insns/vmseq_vx.h
+++ b/riscv/insns/vmseq_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP_CMP
 ({
   res = rs1 == vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmsgt_vi.h b/riscv/insns/vmsgt_vi.h
index 2986082..4f7dea8 100644
--- a/riscv/insns/vmsgt_vi.h
+++ b/riscv/insns/vmsgt_vi.h
@@ -3,4 +3,3 @@ VI_VI_LOOP_CMP
 ({
   res = vs2 > simm5;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmsgt_vx.h b/riscv/insns/vmsgt_vx.h
index 5c99f98..5f24db6 100644
--- a/riscv/insns/vmsgt_vx.h
+++ b/riscv/insns/vmsgt_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP_CMP
 ({
   res = vs2 > rs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmsgtu_vi.h b/riscv/insns/vmsgtu_vi.h
index cef764e..268d437 100644
--- a/riscv/insns/vmsgtu_vi.h
+++ b/riscv/insns/vmsgtu_vi.h
@@ -3,4 +3,3 @@ VI_VI_ULOOP_CMP
 ({
   res = vs2 > simm5;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmsgtu_vx.h b/riscv/insns/vmsgtu_vx.h
index 03713e3..7f39800 100644
--- a/riscv/insns/vmsgtu_vx.h
+++ b/riscv/insns/vmsgtu_vx.h
@@ -3,4 +3,3 @@ VI_VX_ULOOP_CMP
 ({
   res = vs2 > rs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmsif_m.h b/riscv/insns/vmsif_m.h
index 4286691..826e7cd 100644
--- a/riscv/insns/vmsif_m.h
+++ b/riscv/insns/vmsif_m.h
@@ -32,4 +32,3 @@ for (reg_t i = P.VU.vstart ; i < vl; ++i) {
 
 VI_TAIL_ZERO_MASK(rd_num);
 P.VU.vstart = 0;
-VI_CHECK_1905
diff --git a/riscv/insns/vmsle_vi.h b/riscv/insns/vmsle_vi.h
index 13546df..f0f67d0 100644
--- a/riscv/insns/vmsle_vi.h
+++ b/riscv/insns/vmsle_vi.h
@@ -3,4 +3,3 @@ VI_VI_LOOP_CMP
 ({
   res = vs2 <= simm5;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmsle_vv.h b/riscv/insns/vmsle_vv.h
index 05d8273..30aba06 100644
--- a/riscv/insns/vmsle_vv.h
+++ b/riscv/insns/vmsle_vv.h
@@ -3,4 +3,3 @@ VI_VV_LOOP_CMP
 ({
   res = vs2 <= vs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmsle_vx.h b/riscv/insns/vmsle_vx.h
index bce3ace..c26d596 100644
--- a/riscv/insns/vmsle_vx.h
+++ b/riscv/insns/vmsle_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP_CMP
 ({
   res = vs2 <= rs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmsleu_vi.h b/riscv/insns/vmsleu_vi.h
index 9c8ef0b..dc4fd18 100644
--- a/riscv/insns/vmsleu_vi.h
+++ b/riscv/insns/vmsleu_vi.h
@@ -3,4 +3,3 @@ VI_VI_ULOOP_CMP
 ({
   res = vs2 <= simm5;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmsleu_vv.h b/riscv/insns/vmsleu_vv.h
index 4cb19f4..0e46032 100644
--- a/riscv/insns/vmsleu_vv.h
+++ b/riscv/insns/vmsleu_vv.h
@@ -3,4 +3,3 @@ VI_VV_ULOOP_CMP
 ({
   res = vs2 <= vs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmsleu_vx.h b/riscv/insns/vmsleu_vx.h
index aeecdf3..935b176 100644
--- a/riscv/insns/vmsleu_vx.h
+++ b/riscv/insns/vmsleu_vx.h
@@ -3,4 +3,3 @@ VI_VX_ULOOP_CMP
 ({
   res = vs2 <= rs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmslt_vv.h b/riscv/insns/vmslt_vv.h
index 323a216..71e6f87 100644
--- a/riscv/insns/vmslt_vv.h
+++ b/riscv/insns/vmslt_vv.h
@@ -3,4 +3,3 @@ VI_VV_LOOP_CMP
 ({
   res = vs2 < vs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmslt_vx.h b/riscv/insns/vmslt_vx.h
index 7e96018..b32bb14 100644
--- a/riscv/insns/vmslt_vx.h
+++ b/riscv/insns/vmslt_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP_CMP
 ({
   res = vs2 < rs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmsltu_vv.h b/riscv/insns/vmsltu_vv.h
index 4f403dc..53a570a 100644
--- a/riscv/insns/vmsltu_vv.h
+++ b/riscv/insns/vmsltu_vv.h
@@ -3,4 +3,3 @@ VI_VV_ULOOP_CMP
 ({
   res = vs2 < vs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmsltu_vx.h b/riscv/insns/vmsltu_vx.h
index 7d7e98a..8082544 100644
--- a/riscv/insns/vmsltu_vx.h
+++ b/riscv/insns/vmsltu_vx.h
@@ -3,4 +3,3 @@ VI_VX_ULOOP_CMP
 ({
   res = vs2 < rs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmsne_vi.h b/riscv/insns/vmsne_vi.h
index c515c33..5e9758e 100644
--- a/riscv/insns/vmsne_vi.h
+++ b/riscv/insns/vmsne_vi.h
@@ -3,4 +3,3 @@ VI_VI_LOOP_CMP
 ({
   res = vs2 != simm5;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmsne_vv.h b/riscv/insns/vmsne_vv.h
index b62bc50..e6a7174 100644
--- a/riscv/insns/vmsne_vv.h
+++ b/riscv/insns/vmsne_vv.h
@@ -3,4 +3,3 @@ VI_VV_LOOP_CMP
 ({
   res = vs2 != vs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmsne_vx.h b/riscv/insns/vmsne_vx.h
index 6b5ba31..9e4c155 100644
--- a/riscv/insns/vmsne_vx.h
+++ b/riscv/insns/vmsne_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP_CMP
 ({
   res = vs2 != rs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmsof_m.h b/riscv/insns/vmsof_m.h
index e997973..48805f7 100644
--- a/riscv/insns/vmsof_m.h
+++ b/riscv/insns/vmsof_m.h
@@ -30,4 +30,3 @@ for (reg_t i = P.VU.vstart ; i < vl; ++i) {
 
 VI_TAIL_ZERO_MASK(rd_num);
 P.VU.vstart = 0;
-VI_CHECK_1905
diff --git a/riscv/insns/vmul_vv.h b/riscv/insns/vmul_vv.h
index da0b12f..a327817 100644
--- a/riscv/insns/vmul_vv.h
+++ b/riscv/insns/vmul_vv.h
@@ -3,4 +3,3 @@ VI_VV_LOOP
 ({
   vd = vs2 * vs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmul_vx.h b/riscv/insns/vmul_vx.h
index 1b1b5be..8d68390 100644
--- a/riscv/insns/vmul_vx.h
+++ b/riscv/insns/vmul_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP
 ({
   vd = vs2 * rs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmulh_vv.h b/riscv/insns/vmulh_vv.h
index a558433..e861a33 100644
--- a/riscv/insns/vmulh_vv.h
+++ b/riscv/insns/vmulh_vv.h
@@ -3,4 +3,3 @@ VI_VV_LOOP
 ({
   vd = ((int128_t)vs2 * vs1) >> sew;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmulh_vx.h b/riscv/insns/vmulh_vx.h
index f8eb54c..b6b5503 100644
--- a/riscv/insns/vmulh_vx.h
+++ b/riscv/insns/vmulh_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP
 ({
   vd = ((int128_t)vs2 * rs1) >> sew;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmulhsu_vv.h b/riscv/insns/vmulhsu_vv.h
index c3d5c3e..59882da 100644
--- a/riscv/insns/vmulhsu_vv.h
+++ b/riscv/insns/vmulhsu_vv.h
@@ -35,4 +35,3 @@ default: {
 }
 }
 VI_LOOP_END
-VI_CHECK_1905
diff --git a/riscv/insns/vmulhsu_vx.h b/riscv/insns/vmulhsu_vx.h
index 4974054..d39615a 100644
--- a/riscv/insns/vmulhsu_vx.h
+++ b/riscv/insns/vmulhsu_vx.h
@@ -35,4 +35,3 @@ default: {
 }
 }
 VI_LOOP_END
-VI_CHECK_1905
diff --git a/riscv/insns/vmulhu_vv.h b/riscv/insns/vmulhu_vv.h
index 0cac46f..8e318ed 100644
--- a/riscv/insns/vmulhu_vv.h
+++ b/riscv/insns/vmulhu_vv.h
@@ -3,4 +3,3 @@ VI_VV_ULOOP
 ({
   vd = ((uint128_t)vs2 * vs1) >> sew;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vmulhu_vx.h b/riscv/insns/vmulhu_vx.h
index 096e0b2..672ad32 100644
--- a/riscv/insns/vmulhu_vx.h
+++ b/riscv/insns/vmulhu_vx.h
@@ -3,4 +3,3 @@ VI_VX_ULOOP
 ({
   vd = ((uint128_t)vs2 * rs1) >> sew;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vnclip_vi.h b/riscv/insns/vnclip_vi.h
index 4d0ba40..ca27593 100644
--- a/riscv/insns/vnclip_vi.h
+++ b/riscv/insns/vnclip_vi.h
@@ -22,4 +22,3 @@ VI_VVXI_LOOP_NARROW
 
   vd = result;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vnclip_vv.h b/riscv/insns/vnclip_vv.h
index a6476e4..7bcb4cb 100644
--- a/riscv/insns/vnclip_vv.h
+++ b/riscv/insns/vnclip_vv.h
@@ -28,4 +28,3 @@ VI_VVXI_LOOP_NARROW
 
   vd = result;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vnclip_vx.h b/riscv/insns/vnclip_vx.h
index 5212650..b66e830 100644
--- a/riscv/insns/vnclip_vx.h
+++ b/riscv/insns/vnclip_vx.h
@@ -27,4 +27,3 @@ VI_VVXI_LOOP_NARROW
 
   vd = result;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vnclipu_vi.h b/riscv/insns/vnclipu_vi.h
index fd3c488..61cb015 100644
--- a/riscv/insns/vnclipu_vi.h
+++ b/riscv/insns/vnclipu_vi.h
@@ -18,4 +18,3 @@ VI_VVXI_LOOP_NARROW
 
   vd = result;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vnclipu_vv.h b/riscv/insns/vnclipu_vv.h
index aab212a..004f24f 100644
--- a/riscv/insns/vnclipu_vv.h
+++ b/riscv/insns/vnclipu_vv.h
@@ -24,4 +24,3 @@ VI_VVXI_LOOP_NARROW
 
   vd = result;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vnclipu_vx.h b/riscv/insns/vnclipu_vx.h
index e0e8ccb..0507a2b 100644
--- a/riscv/insns/vnclipu_vx.h
+++ b/riscv/insns/vnclipu_vx.h
@@ -24,4 +24,3 @@ VI_VVXI_LOOP_NARROW
 
   vd = result;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vnmsac_vv.h b/riscv/insns/vnmsac_vv.h
index 6915892..7c10f29 100644
--- a/riscv/insns/vnmsac_vv.h
+++ b/riscv/insns/vnmsac_vv.h
@@ -3,4 +3,3 @@ VI_VV_LOOP
 ({
   vd = -(vs1 * vs2) + vd;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vnmsac_vx.h b/riscv/insns/vnmsac_vx.h
index 8d05a89..44920be 100644
--- a/riscv/insns/vnmsac_vx.h
+++ b/riscv/insns/vnmsac_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP
 ({
   vd = -(rs1 * vs2) + vd;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vnmsub_vv.h b/riscv/insns/vnmsub_vv.h
index 2aa4b05..37f8228 100644
--- a/riscv/insns/vnmsub_vv.h
+++ b/riscv/insns/vnmsub_vv.h
@@ -3,4 +3,3 @@ VI_VV_LOOP
 ({
   vd = -(vd * vs1) + vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vnmsub_vx.h b/riscv/insns/vnmsub_vx.h
index 9b09f4d..2e00d22 100644
--- a/riscv/insns/vnmsub_vx.h
+++ b/riscv/insns/vnmsub_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP
 ({
   vd = -(vd * rs1) + vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vnsra_vi.h b/riscv/insns/vnsra_vi.h
index 3191840..0502ff1 100644
--- a/riscv/insns/vnsra_vi.h
+++ b/riscv/insns/vnsra_vi.h
@@ -3,4 +3,3 @@ VI_VI_LOOP_NSHIFT
 ({
   vd = vs2 >> (zimm5 & (sew * 2 - 1) & 0x1f);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vnsra_vv.h b/riscv/insns/vnsra_vv.h
index 810fd05..555ce3f 100644
--- a/riscv/insns/vnsra_vv.h
+++ b/riscv/insns/vnsra_vv.h
@@ -3,4 +3,3 @@ VI_VV_LOOP_NSHIFT
 ({
   vd = vs2 >> (vs1 & (sew * 2 - 1));
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vnsra_vx.h b/riscv/insns/vnsra_vx.h
index 085d918..05a55e3 100644
--- a/riscv/insns/vnsra_vx.h
+++ b/riscv/insns/vnsra_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP_NSHIFT
 ({
   vd = vs2 >> (rs1 & (sew * 2 - 1));
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vnsrl_vi.h b/riscv/insns/vnsrl_vi.h
index 959c24b..d4dfcf0 100644
--- a/riscv/insns/vnsrl_vi.h
+++ b/riscv/insns/vnsrl_vi.h
@@ -3,4 +3,3 @@ VI_VI_LOOP_NSHIFT
 ({
   vd = vs2_u >> (zimm5 & (sew * 2 - 1));
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vnsrl_vv.h b/riscv/insns/vnsrl_vv.h
index ee158f4..ab72b84 100644
--- a/riscv/insns/vnsrl_vv.h
+++ b/riscv/insns/vnsrl_vv.h
@@ -3,4 +3,3 @@ VI_VV_LOOP_NSHIFT
 ({
   vd = vs2_u >> (vs1 & (sew * 2 - 1));
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vnsrl_vx.h b/riscv/insns/vnsrl_vx.h
index 14e073f..e149b38 100644
--- a/riscv/insns/vnsrl_vx.h
+++ b/riscv/insns/vnsrl_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP_NSHIFT
 ({
   vd = vs2_u >> (rs1 & (sew * 2 - 1));
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vor_vi.h b/riscv/insns/vor_vi.h
index c725de9..f759607 100644
--- a/riscv/insns/vor_vi.h
+++ b/riscv/insns/vor_vi.h
@@ -3,4 +3,3 @@ VI_VI_LOOP
 ({
   vd = simm5 | vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vor_vv.h b/riscv/insns/vor_vv.h
index b11360f..0c46066 100644
--- a/riscv/insns/vor_vv.h
+++ b/riscv/insns/vor_vv.h
@@ -3,4 +3,3 @@ VI_VV_LOOP
 ({
   vd = vs1 | vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vor_vx.h b/riscv/insns/vor_vx.h
index 8004901..01c003a 100644
--- a/riscv/insns/vor_vx.h
+++ b/riscv/insns/vor_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP
 ({
   vd = rs1 | vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vpopc_m.h b/riscv/insns/vpopc_m.h
index fed4209..de50943 100644
--- a/riscv/insns/vpopc_m.h
+++ b/riscv/insns/vpopc_m.h
@@ -22,4 +22,3 @@ for (reg_t i=P.VU.vstart; i<vl; ++i) {
 }
 P.VU.vstart = 0;
 WRITE_RD(popcount);
-VI_CHECK_1905
diff --git a/riscv/insns/vredand_vs.h b/riscv/insns/vredand_vs.h
index 22e5dfd..6c2d908 100644
--- a/riscv/insns/vredand_vs.h
+++ b/riscv/insns/vredand_vs.h
@@ -3,4 +3,3 @@ VI_VV_LOOP_REDUCTION
 ({
   vd_0_res &= vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vredmax_vs.h b/riscv/insns/vredmax_vs.h
index 8689744..be2e76a 100644
--- a/riscv/insns/vredmax_vs.h
+++ b/riscv/insns/vredmax_vs.h
@@ -3,4 +3,3 @@ VI_VV_LOOP_REDUCTION
 ({
   vd_0_res = (vd_0_res >= vs2) ? vd_0_res : vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vredmaxu_vs.h b/riscv/insns/vredmaxu_vs.h
index c281646..960f486 100644
--- a/riscv/insns/vredmaxu_vs.h
+++ b/riscv/insns/vredmaxu_vs.h
@@ -3,4 +3,3 @@ VI_VV_ULOOP_REDUCTION
 ({
   vd_0_res = (vd_0_res >= vs2) ? vd_0_res : vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vredmin_vs.h b/riscv/insns/vredmin_vs.h
index a21644b..50359b7 100644
--- a/riscv/insns/vredmin_vs.h
+++ b/riscv/insns/vredmin_vs.h
@@ -3,4 +3,3 @@ VI_VV_LOOP_REDUCTION
 ({
   vd_0_res = (vd_0_res <= vs2) ? vd_0_res : vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vredminu_vs.h b/riscv/insns/vredminu_vs.h
index 40ff07a..7082475 100644
--- a/riscv/insns/vredminu_vs.h
+++ b/riscv/insns/vredminu_vs.h
@@ -3,4 +3,3 @@ VI_VV_ULOOP_REDUCTION
 ({
   vd_0_res = (vd_0_res <= vs2) ? vd_0_res : vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vredor_vs.h b/riscv/insns/vredor_vs.h
index ccd2981..f7acd9a 100644
--- a/riscv/insns/vredor_vs.h
+++ b/riscv/insns/vredor_vs.h
@@ -3,4 +3,3 @@ VI_VV_LOOP_REDUCTION
 ({
   vd_0_res |= vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vredsum_vs.h b/riscv/insns/vredsum_vs.h
index 3bca23a..c4fefe5 100644
--- a/riscv/insns/vredsum_vs.h
+++ b/riscv/insns/vredsum_vs.h
@@ -3,4 +3,3 @@ VI_VV_LOOP_REDUCTION
 ({
   vd_0_res += vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vredxor_vs.h b/riscv/insns/vredxor_vs.h
index ad4b015..bb81ad9 100644
--- a/riscv/insns/vredxor_vs.h
+++ b/riscv/insns/vredxor_vs.h
@@ -3,4 +3,3 @@ VI_VV_LOOP_REDUCTION
 ({
   vd_0_res ^= vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vrem_vv.h b/riscv/insns/vrem_vv.h
index e3a184a..da477f0 100644
--- a/riscv/insns/vrem_vv.h
+++ b/riscv/insns/vrem_vv.h
@@ -9,4 +9,3 @@ VI_VV_LOOP
     vd = vs2 % vs1;
   }
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vrem_vx.h b/riscv/insns/vrem_vx.h
index 9e94a34..f068842 100644
--- a/riscv/insns/vrem_vx.h
+++ b/riscv/insns/vrem_vx.h
@@ -8,4 +8,3 @@ VI_VX_LOOP
   else
     vd = vs2 % rs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vremu_vv.h b/riscv/insns/vremu_vv.h
index f773a59..7e15072 100644
--- a/riscv/insns/vremu_vv.h
+++ b/riscv/insns/vremu_vv.h
@@ -6,4 +6,3 @@ VI_VV_ULOOP
   else
     vd = vs2 % vs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vremu_vx.h b/riscv/insns/vremu_vx.h
index a9fdb28..a87a820 100644
--- a/riscv/insns/vremu_vx.h
+++ b/riscv/insns/vremu_vx.h
@@ -6,4 +6,3 @@ VI_VX_ULOOP
   else
     vd = vs2 % rs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vrgather_vi.h b/riscv/insns/vrgather_vi.h
index 827f975..eff67b8 100644
--- a/riscv/insns/vrgather_vi.h
+++ b/riscv/insns/vrgather_vi.h
@@ -27,4 +27,3 @@ for (reg_t i = P.VU.vstart; i < vl; ++i) {
 
 VI_TAIL_ZERO(1);
 P.VU.vstart = 0;
-VI_CHECK_1905
diff --git a/riscv/insns/vrgather_vv.h b/riscv/insns/vrgather_vv.h
index 6338f61..ce0c2a6 100644
--- a/riscv/insns/vrgather_vv.h
+++ b/riscv/insns/vrgather_vv.h
@@ -37,4 +37,3 @@ for (reg_t i = P.VU.vstart; i < vl; ++i) {
 
 VI_TAIL_ZERO(1);
 P.VU.vstart = 0;
-VI_CHECK_1905
diff --git a/riscv/insns/vrgather_vx.h b/riscv/insns/vrgather_vx.h
index 2e2ccb1..e9ff3b1 100644
--- a/riscv/insns/vrgather_vx.h
+++ b/riscv/insns/vrgather_vx.h
@@ -28,4 +28,3 @@ for (reg_t i = P.VU.vstart; i < vl; ++i) {
 
 VI_TAIL_ZERO(1);
 P.VU.vstart = 0;
-VI_CHECK_1905
diff --git a/riscv/insns/vrsub_vi.h b/riscv/insns/vrsub_vi.h
index 40adde9..198c33f 100644
--- a/riscv/insns/vrsub_vi.h
+++ b/riscv/insns/vrsub_vi.h
@@ -3,4 +3,3 @@ VI_VI_LOOP
 ({
   vd = simm5 - vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vrsub_vx.h b/riscv/insns/vrsub_vx.h
index 31d42e9..bfd6259 100644
--- a/riscv/insns/vrsub_vx.h
+++ b/riscv/insns/vrsub_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP
 ({
   vd = rs1 - vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vsadd_vi.h b/riscv/insns/vsadd_vi.h
index 10d4cbf..de2cb83 100644
--- a/riscv/insns/vsadd_vi.h
+++ b/riscv/insns/vsadd_vi.h
@@ -25,4 +25,3 @@ default: {
 }
 P.VU.vxsat |= sat;
 VI_LOOP_END
-VI_CHECK_1905
diff --git a/riscv/insns/vsadd_vv.h b/riscv/insns/vsadd_vv.h
index bf4fd04..2152bab 100644
--- a/riscv/insns/vsadd_vv.h
+++ b/riscv/insns/vsadd_vv.h
@@ -26,4 +26,3 @@ default: {
 P.VU.vxsat |= sat;
 VI_LOOP_END
 
-VI_CHECK_1905
diff --git a/riscv/insns/vsadd_vx.h b/riscv/insns/vsadd_vx.h
index 9ffa822..781e9e8 100644
--- a/riscv/insns/vsadd_vx.h
+++ b/riscv/insns/vsadd_vx.h
@@ -25,4 +25,3 @@ default: {
 }
 P.VU.vxsat |= sat;
 VI_LOOP_END
-VI_CHECK_1905
diff --git a/riscv/insns/vsaddu_vi.h b/riscv/insns/vsaddu_vi.h
index 0a108da..9d376cc 100644
--- a/riscv/insns/vsaddu_vi.h
+++ b/riscv/insns/vsaddu_vi.h
@@ -9,4 +9,3 @@ VI_VI_ULOOP
 
   P.VU.vxsat |= sat;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vsaddu_vv.h b/riscv/insns/vsaddu_vv.h
index d29ee06..e5d7025 100644
--- a/riscv/insns/vsaddu_vv.h
+++ b/riscv/insns/vsaddu_vv.h
@@ -9,4 +9,3 @@ VI_VV_ULOOP
 
   P.VU.vxsat |= sat;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vsaddu_vx.h b/riscv/insns/vsaddu_vx.h
index 7747409..46ec29d 100644
--- a/riscv/insns/vsaddu_vx.h
+++ b/riscv/insns/vsaddu_vx.h
@@ -10,4 +10,3 @@ VI_VX_ULOOP
   P.VU.vxsat |= sat;
 
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vsb_v.h b/riscv/insns/vsb_v.h
index 8ce9a13..d8c9090 100644
--- a/riscv/insns/vsb_v.h
+++ b/riscv/insns/vsb_v.h
@@ -1,4 +1,3 @@
 // vsb.v and vsseg[2-8]b.v
 require(P.VU.vsew >= e8);
 VI_ST(0, i * nf + fn, uint8, 1);
-VI_CHECK_1905
diff --git a/riscv/insns/vsbc_vvm.h b/riscv/insns/vsbc_vvm.h
index 0c55818..4cd58ba 100644
--- a/riscv/insns/vsbc_vvm.h
+++ b/riscv/insns/vsbc_vvm.h
@@ -9,4 +9,3 @@ VI_VV_LOOP
   uint128_t res = (op_mask & vs1) - (op_mask & vs2) - carry;
   vd = res;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vsbc_vxm.h b/riscv/insns/vsbc_vxm.h
index 2dd38c5..12551b8 100644
--- a/riscv/insns/vsbc_vxm.h
+++ b/riscv/insns/vsbc_vxm.h
@@ -9,4 +9,3 @@ VI_VX_ULOOP
   uint128_t res = (op_mask & rs1) - (op_mask & vs2) - carry;
   vd = res;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vse_v.h b/riscv/insns/vse_v.h
index be473f5..1e0dac3 100644
--- a/riscv/insns/vse_v.h
+++ b/riscv/insns/vse_v.h
@@ -11,4 +11,3 @@ if (sew == e8) {
   VI_ST(0, (i * nf + fn), uint64, 8);
 }
 
-VI_CHECK_1905
diff --git a/riscv/insns/vsh_v.h b/riscv/insns/vsh_v.h
index 78f70fb..a38bc90 100644
--- a/riscv/insns/vsh_v.h
+++ b/riscv/insns/vsh_v.h
@@ -1,4 +1,3 @@
 // vsh.v and vsseg[2-8]h.v
 require(P.VU.vsew >= e16);
 VI_ST(0, i * nf + fn, uint16, 2);
-VI_CHECK_1905
diff --git a/riscv/insns/vslide1up_vx.h b/riscv/insns/vslide1up_vx.h
index 10c2ed6..50cc503 100644
--- a/riscv/insns/vslide1up_vx.h
+++ b/riscv/insns/vslide1up_vx.h
@@ -30,4 +30,3 @@ if (i != 0) {
   }
 }
 VI_LOOP_END
-VI_CHECK_1905
diff --git a/riscv/insns/vslideup_vi.h b/riscv/insns/vslideup_vi.h
index 4750ade..4135b20 100644
--- a/riscv/insns/vslideup_vi.h
+++ b/riscv/insns/vslideup_vi.h
@@ -31,4 +31,3 @@ default: {
 break;
 }
 VI_LOOP_END
-VI_CHECK_1905
diff --git a/riscv/insns/vslideup_vx.h b/riscv/insns/vslideup_vx.h
index e89eef1..bf73fcd 100644
--- a/riscv/insns/vslideup_vx.h
+++ b/riscv/insns/vslideup_vx.h
@@ -27,4 +27,3 @@ default: {
 break;
 }
 VI_LOOP_END
-VI_CHECK_1905
diff --git a/riscv/insns/vsll_vi.h b/riscv/insns/vsll_vi.h
index d4eeabb..be46506 100644
--- a/riscv/insns/vsll_vi.h
+++ b/riscv/insns/vsll_vi.h
@@ -3,4 +3,3 @@ VI_VI_LOOP
 ({
   vd = vs2 << (simm5 & (sew - 1) & 0x1f);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vsll_vv.h b/riscv/insns/vsll_vv.h
index ddfeae0..ce82022 100644
--- a/riscv/insns/vsll_vv.h
+++ b/riscv/insns/vsll_vv.h
@@ -3,4 +3,3 @@ VI_VV_LOOP
 ({
   vd = vs2 << (vs1 & (sew - 1));
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vsll_vx.h b/riscv/insns/vsll_vx.h
index d3127e4..823510b 100644
--- a/riscv/insns/vsll_vx.h
+++ b/riscv/insns/vsll_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP
 ({
   vd = vs2 << (rs1 & (sew - 1));
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vsmul_vv.h b/riscv/insns/vsmul_vv.h
index 421cadf..a0c7f99 100644
--- a/riscv/insns/vsmul_vv.h
+++ b/riscv/insns/vsmul_vv.h
@@ -31,4 +31,3 @@ VI_VV_ULOOP
   }
   vd = result;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vsmul_vx.h b/riscv/insns/vsmul_vx.h
index b52d01f..c7909c7 100644
--- a/riscv/insns/vsmul_vx.h
+++ b/riscv/insns/vsmul_vx.h
@@ -32,4 +32,3 @@ VI_VX_ULOOP
   }
   vd = result;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vsra_vi.h b/riscv/insns/vsra_vi.h
index e8f0499..5c58927 100644
--- a/riscv/insns/vsra_vi.h
+++ b/riscv/insns/vsra_vi.h
@@ -3,4 +3,3 @@ VI_VI_LOOP
 ({
   vd = vs2 >> (simm5 & (sew - 1) & 0x1f);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vsra_vv.h b/riscv/insns/vsra_vv.h
index 51faae7..8889af9 100644
--- a/riscv/insns/vsra_vv.h
+++ b/riscv/insns/vsra_vv.h
@@ -3,4 +3,3 @@ VI_VV_LOOP
 ({
   vd = vs2 >> (vs1 & (sew - 1));
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vsra_vx.h b/riscv/insns/vsra_vx.h
index 9f4248e..c1b0c10 100644
--- a/riscv/insns/vsra_vx.h
+++ b/riscv/insns/vsra_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP
 ({
   vd = vs2 >> (rs1 & (sew - 1));
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vsrl_vi.h b/riscv/insns/vsrl_vi.h
index 6e5fbcf..5006854 100644
--- a/riscv/insns/vsrl_vi.h
+++ b/riscv/insns/vsrl_vi.h
@@ -3,4 +3,3 @@ VI_VI_ULOOP
 ({
   vd = vs2 >> (simm5 & (sew - 1) & 0x1f);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vsrl_vv.h b/riscv/insns/vsrl_vv.h
index bb6ff6b..6376af3 100644
--- a/riscv/insns/vsrl_vv.h
+++ b/riscv/insns/vsrl_vv.h
@@ -3,4 +3,3 @@ VI_VV_ULOOP
 ({
   vd = vs2 >> (vs1 & (sew - 1));
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vsrl_vx.h b/riscv/insns/vsrl_vx.h
index 74b4868..a4f899c 100644
--- a/riscv/insns/vsrl_vx.h
+++ b/riscv/insns/vsrl_vx.h
@@ -3,4 +3,3 @@ VI_VX_ULOOP
 ({
   vd = vs2 >> (rs1 & (sew - 1));
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vssb_v.h b/riscv/insns/vssb_v.h
index ae42a9b..1bf0ecf 100644
--- a/riscv/insns/vssb_v.h
+++ b/riscv/insns/vssb_v.h
@@ -1,4 +1,3 @@
 // vssb.v and vssseg[2-8]b.v
 require(P.VU.vsew >= e8);
 VI_ST(i * RS2, fn, uint8, 1);
-VI_CHECK_1905
diff --git a/riscv/insns/vsse_v.h b/riscv/insns/vsse_v.h
index 2b48a6e..2242759 100644
--- a/riscv/insns/vsse_v.h
+++ b/riscv/insns/vsse_v.h
@@ -11,4 +11,3 @@ if (sew == e8) {
   VI_ST(i * RS2, fn, uint64, 8);
 }
 
-VI_CHECK_1905
diff --git a/riscv/insns/vssh_v.h b/riscv/insns/vssh_v.h
index 38573c8..e0ebed2 100644
--- a/riscv/insns/vssh_v.h
+++ b/riscv/insns/vssh_v.h
@@ -1,4 +1,3 @@
 // vssh.v and vssseg[2-8]h.v
 require(P.VU.vsew >= e16);
 VI_ST(i * RS2, fn, uint16, 2);
-VI_CHECK_1905
diff --git a/riscv/insns/vssra_vi.h b/riscv/insns/vssra_vi.h
index 21aba63..ef2390c 100644
--- a/riscv/insns/vssra_vi.h
+++ b/riscv/insns/vssra_vi.h
@@ -6,4 +6,3 @@ VI_VI_LOOP
   INT_ROUNDING(vs2, xrm, sh);
   vd = vs2 >> sh;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vssra_vv.h b/riscv/insns/vssra_vv.h
index a9aa51b..e697b52 100644
--- a/riscv/insns/vssra_vv.h
+++ b/riscv/insns/vssra_vv.h
@@ -7,4 +7,3 @@ VI_VV_LOOP
   INT_ROUNDING(vs2, xrm, sh);
   vd = vs2 >> sh;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vssra_vx.h b/riscv/insns/vssra_vx.h
index e0c54e9..8d7ad20 100644
--- a/riscv/insns/vssra_vx.h
+++ b/riscv/insns/vssra_vx.h
@@ -7,4 +7,3 @@ VI_VX_LOOP
   INT_ROUNDING(vs2, xrm, sh);
   vd = vs2 >> sh;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vssrl_vi.h b/riscv/insns/vssrl_vi.h
index 85e5234..8a10df0 100644
--- a/riscv/insns/vssrl_vi.h
+++ b/riscv/insns/vssrl_vi.h
@@ -7,4 +7,3 @@ VI_VI_ULOOP
   INT_ROUNDING(vs2, xrm, sh);
   vd = vs2 >> sh;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vssrl_vv.h b/riscv/insns/vssrl_vv.h
index 1b66ef3..f40cd90 100644
--- a/riscv/insns/vssrl_vv.h
+++ b/riscv/insns/vssrl_vv.h
@@ -7,4 +7,3 @@ VI_VV_ULOOP
   INT_ROUNDING(vs2, xrm, sh);
   vd = vs2 >> sh;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vssrl_vx.h b/riscv/insns/vssrl_vx.h
index 675c985..5da3f75 100644
--- a/riscv/insns/vssrl_vx.h
+++ b/riscv/insns/vssrl_vx.h
@@ -7,4 +7,3 @@ VI_VX_ULOOP
   INT_ROUNDING(vs2, xrm, sh);
   vd = vs2 >> sh;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vssub_vv.h b/riscv/insns/vssub_vv.h
index bcb12cc..fd3ee21 100644
--- a/riscv/insns/vssub_vv.h
+++ b/riscv/insns/vssub_vv.h
@@ -26,4 +26,3 @@ default: {
 }
 P.VU.vxsat |= sat;
 VI_LOOP_END
-VI_CHECK_1905
diff --git a/riscv/insns/vssub_vx.h b/riscv/insns/vssub_vx.h
index 40bbf66..5c5c781 100644
--- a/riscv/insns/vssub_vx.h
+++ b/riscv/insns/vssub_vx.h
@@ -26,4 +26,3 @@ default: {
 }
 P.VU.vxsat |= sat;
 VI_LOOP_END
-VI_CHECK_1905
diff --git a/riscv/insns/vssubu_vv.h b/riscv/insns/vssubu_vv.h
index 92dbdaa..c5c74fe 100644
--- a/riscv/insns/vssubu_vv.h
+++ b/riscv/insns/vssubu_vv.h
@@ -27,4 +27,3 @@ default: {
 P.VU.vxsat |= sat;
 
 VI_LOOP_END
-VI_CHECK_1905
diff --git a/riscv/insns/vssubu_vx.h b/riscv/insns/vssubu_vx.h
index 83eb63b..12cfdbb 100644
--- a/riscv/insns/vssubu_vx.h
+++ b/riscv/insns/vssubu_vx.h
@@ -26,4 +26,3 @@ default: {
 }
 P.VU.vxsat |= sat;
 VI_LOOP_END
-VI_CHECK_1905
diff --git a/riscv/insns/vssw_v.h b/riscv/insns/vssw_v.h
index 025b671..c191d2e 100644
--- a/riscv/insns/vssw_v.h
+++ b/riscv/insns/vssw_v.h
@@ -1,4 +1,3 @@
 // vssw.v and vssseg[2-8]w.v
 require(P.VU.vsew >= e32);
 VI_ST(i * RS2, fn, uint32, 4);
-VI_CHECK_1905
diff --git a/riscv/insns/vsub_vv.h b/riscv/insns/vsub_vv.h
index f068e30..7d119d5 100644
--- a/riscv/insns/vsub_vv.h
+++ b/riscv/insns/vsub_vv.h
@@ -3,4 +3,3 @@ VI_VV_LOOP
 ({
   vd = vs2 - vs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vsub_vx.h b/riscv/insns/vsub_vx.h
index dc69870..e075b42 100644
--- a/riscv/insns/vsub_vx.h
+++ b/riscv/insns/vsub_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP
 ({
   vd = vs2 - rs1;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vsuxb_v.h b/riscv/insns/vsuxb_v.h
index f12c456..286d653 100644
--- a/riscv/insns/vsuxb_v.h
+++ b/riscv/insns/vsuxb_v.h
@@ -36,4 +36,3 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) {
   }
 }
 P.VU.vstart = 0;
-VI_CHECK_1905
diff --git a/riscv/insns/vsuxe_v.h b/riscv/insns/vsuxe_v.h
index d0c1f36..c51d605 100644
--- a/riscv/insns/vsuxe_v.h
+++ b/riscv/insns/vsuxe_v.h
@@ -37,4 +37,3 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) {
   }
 }
 P.VU.vstart = 0;
-VI_CHECK_1905
diff --git a/riscv/insns/vsuxh_v.h b/riscv/insns/vsuxh_v.h
index e237306..9858a61 100644
--- a/riscv/insns/vsuxh_v.h
+++ b/riscv/insns/vsuxh_v.h
@@ -31,4 +31,3 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) {
   }
 }
 P.VU.vstart = 0;
-VI_CHECK_1905
diff --git a/riscv/insns/vsuxw_v.h b/riscv/insns/vsuxw_v.h
index bc9fc6c..e9e4b7c 100644
--- a/riscv/insns/vsuxw_v.h
+++ b/riscv/insns/vsuxw_v.h
@@ -26,4 +26,3 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) {
   }
 }
 P.VU.vstart = 0;
-VI_CHECK_1905
diff --git a/riscv/insns/vsw_v.h b/riscv/insns/vsw_v.h
index 69758dc..5066657 100644
--- a/riscv/insns/vsw_v.h
+++ b/riscv/insns/vsw_v.h
@@ -1,6 +1,3 @@
 // vsw.v and vsseg[2-8]w.v
 require(P.VU.vsew >= e32);
 VI_ST(0, i * nf + fn, uint32, 4);
-if (nf >= 2) {
-  VI_CHECK_1905;
-}
diff --git a/riscv/insns/vsxb_v.h b/riscv/insns/vsxb_v.h
index 50f62ae..3e50597 100644
--- a/riscv/insns/vsxb_v.h
+++ b/riscv/insns/vsxb_v.h
@@ -2,4 +2,3 @@
 require(P.VU.vsew >= e8);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
 VI_ST(index[i], fn, uint8, 1);
-VI_CHECK_1905
diff --git a/riscv/insns/vsxe_v.h b/riscv/insns/vsxe_v.h
index 5442480..28984ac 100644
--- a/riscv/insns/vsxe_v.h
+++ b/riscv/insns/vsxe_v.h
@@ -12,4 +12,3 @@ if (sew == e8) {
   VI_ST(index[i], fn, uint64, 8);
 }
 
-VI_CHECK_1905
diff --git a/riscv/insns/vsxh_v.h b/riscv/insns/vsxh_v.h
index 758a0a2..2e5506a 100644
--- a/riscv/insns/vsxh_v.h
+++ b/riscv/insns/vsxh_v.h
@@ -2,4 +2,3 @@
 require(P.VU.vsew >= e16);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
 VI_ST(index[i], fn, uint16, 2);
-VI_CHECK_1905
diff --git a/riscv/insns/vsxw_v.h b/riscv/insns/vsxw_v.h
index 2fd9cfd..9a2119f 100644
--- a/riscv/insns/vsxw_v.h
+++ b/riscv/insns/vsxw_v.h
@@ -2,4 +2,3 @@
 require(P.VU.vsew >= e32);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
 VI_ST(index[i], fn, uint32, 4);
-VI_CHECK_1905
diff --git a/riscv/insns/vwadd_vv.h b/riscv/insns/vwadd_vv.h
index 4e1d135..df4a135 100644
--- a/riscv/insns/vwadd_vv.h
+++ b/riscv/insns/vwadd_vv.h
@@ -4,4 +4,3 @@ VI_VV_LOOP_WIDEN
 ({
   VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, +, +, int);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwadd_vx.h b/riscv/insns/vwadd_vx.h
index cddf21b..c226389 100644
--- a/riscv/insns/vwadd_vx.h
+++ b/riscv/insns/vwadd_vx.h
@@ -4,4 +4,3 @@ VI_VX_LOOP_WIDEN
 ({
   VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, +, +, int);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwadd_wv.h b/riscv/insns/vwadd_wv.h
index 07ff0e4..54d2ba4 100644
--- a/riscv/insns/vwadd_wv.h
+++ b/riscv/insns/vwadd_wv.h
@@ -4,4 +4,3 @@ VI_VV_LOOP_WIDEN
 ({
   VI_WIDE_WVX_OP(vs1, +, int);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwadd_wx.h b/riscv/insns/vwadd_wx.h
index b3dce7e..bb4cee5 100644
--- a/riscv/insns/vwadd_wx.h
+++ b/riscv/insns/vwadd_wx.h
@@ -4,4 +4,3 @@ VI_VX_LOOP_WIDEN
 ({
   VI_WIDE_WVX_OP(rs1, +, int);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwaddu_vv.h b/riscv/insns/vwaddu_vv.h
index 72e33be..286ebc8 100644
--- a/riscv/insns/vwaddu_vv.h
+++ b/riscv/insns/vwaddu_vv.h
@@ -4,4 +4,3 @@ VI_VV_LOOP_WIDEN
 ({
   VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, +, +, uint);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwaddu_vx.h b/riscv/insns/vwaddu_vx.h
index 80138b7..61cddfc 100644
--- a/riscv/insns/vwaddu_vx.h
+++ b/riscv/insns/vwaddu_vx.h
@@ -4,4 +4,3 @@ VI_VX_LOOP_WIDEN
 ({
   VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, +, +, uint);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwaddu_wv.h b/riscv/insns/vwaddu_wv.h
index 7476c20..fee8136 100644
--- a/riscv/insns/vwaddu_wv.h
+++ b/riscv/insns/vwaddu_wv.h
@@ -4,4 +4,3 @@ VI_VV_LOOP_WIDEN
 ({
   VI_WIDE_WVX_OP(vs1, +, uint);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwaddu_wx.h b/riscv/insns/vwaddu_wx.h
index 2c8ecdf..0073ac3 100644
--- a/riscv/insns/vwaddu_wx.h
+++ b/riscv/insns/vwaddu_wx.h
@@ -4,4 +4,3 @@ VI_VX_LOOP_WIDEN
 ({
   VI_WIDE_WVX_OP(rs1, +, uint);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwmacc_vv.h b/riscv/insns/vwmacc_vv.h
index ebd30ec..7208c6d 100644
--- a/riscv/insns/vwmacc_vv.h
+++ b/riscv/insns/vwmacc_vv.h
@@ -4,4 +4,3 @@ VI_VV_LOOP_WIDEN
 ({
   VI_WIDE_OP_AND_ASSIGN(vs2, vs1, vd_w, *, +, int);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwmacc_vx.h b/riscv/insns/vwmacc_vx.h
index 7a0bd0b..5ae597a 100644
--- a/riscv/insns/vwmacc_vx.h
+++ b/riscv/insns/vwmacc_vx.h
@@ -4,4 +4,3 @@ VI_VX_LOOP_WIDEN
 ({
   VI_WIDE_OP_AND_ASSIGN(vs2, rs1, vd_w, *, +, int);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwmaccsu_vv.h b/riscv/insns/vwmaccsu_vv.h
index 17e463a..3aa43ef 100644
--- a/riscv/insns/vwmaccsu_vv.h
+++ b/riscv/insns/vwmaccsu_vv.h
@@ -4,4 +4,3 @@ VI_VV_LOOP_WIDEN
 ({
   VI_WIDE_OP_AND_ASSIGN_MIX(vs2, vs1, vd_w, *, +, int, uint, int);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwmaccsu_vx.h b/riscv/insns/vwmaccsu_vx.h
index d94237e..e00a21d 100644
--- a/riscv/insns/vwmaccsu_vx.h
+++ b/riscv/insns/vwmaccsu_vx.h
@@ -4,4 +4,3 @@ VI_VX_LOOP_WIDEN
 ({
   VI_WIDE_OP_AND_ASSIGN_MIX(vs2, rs1, vd_w, *, +, int, uint, int);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwmaccu_vv.h b/riscv/insns/vwmaccu_vv.h
index 14b1df2..2cbdaa3 100644
--- a/riscv/insns/vwmaccu_vv.h
+++ b/riscv/insns/vwmaccu_vv.h
@@ -4,4 +4,3 @@ VI_VV_LOOP_WIDEN
 ({
   VI_WIDE_OP_AND_ASSIGN(vs2, vs1, vd_w, *, +, uint);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwmaccu_vx.h b/riscv/insns/vwmaccu_vx.h
index f3edccc..533297f 100644
--- a/riscv/insns/vwmaccu_vx.h
+++ b/riscv/insns/vwmaccu_vx.h
@@ -4,4 +4,3 @@ VI_VX_LOOP_WIDEN
 ({
   VI_WIDE_OP_AND_ASSIGN(vs2, rs1, vd_w, *, +, uint);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwmaccus_vx.h b/riscv/insns/vwmaccus_vx.h
index 8c86299..5310f0e 100644
--- a/riscv/insns/vwmaccus_vx.h
+++ b/riscv/insns/vwmaccus_vx.h
@@ -4,4 +4,3 @@ VI_VX_LOOP_WIDEN
 ({
   VI_WIDE_OP_AND_ASSIGN_MIX(vs2, rs1, vd_w, *, +, int, int, uint);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwmul_vv.h b/riscv/insns/vwmul_vv.h
index 5c73891..2197edb 100644
--- a/riscv/insns/vwmul_vv.h
+++ b/riscv/insns/vwmul_vv.h
@@ -4,4 +4,3 @@ VI_VV_LOOP_WIDEN
 ({
   VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, *, +, int);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwmul_vx.h b/riscv/insns/vwmul_vx.h
index bf3a6dd..bc1422d 100644
--- a/riscv/insns/vwmul_vx.h
+++ b/riscv/insns/vwmul_vx.h
@@ -4,4 +4,3 @@ VI_VX_LOOP_WIDEN
 ({
   VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, *, +, int);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwmulsu_vv.h b/riscv/insns/vwmulsu_vv.h
index 1c6cc22..9786adb 100644
--- a/riscv/insns/vwmulsu_vv.h
+++ b/riscv/insns/vwmulsu_vv.h
@@ -14,4 +14,3 @@ VI_VV_LOOP_WIDEN
     break;
   }
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwmulsu_vx.h b/riscv/insns/vwmulsu_vx.h
index b1a594c..feb1fd1 100644
--- a/riscv/insns/vwmulsu_vx.h
+++ b/riscv/insns/vwmulsu_vx.h
@@ -14,4 +14,3 @@ VI_VX_LOOP_WIDEN
     break;
   }
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwmulu_vv.h b/riscv/insns/vwmulu_vv.h
index 4cbca42..8ddbb4b 100644
--- a/riscv/insns/vwmulu_vv.h
+++ b/riscv/insns/vwmulu_vv.h
@@ -4,4 +4,3 @@ VI_VV_LOOP_WIDEN
 ({
   VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, *, +, uint);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwmulu_vx.h b/riscv/insns/vwmulu_vx.h
index 2270c1f..1ce77ee 100644
--- a/riscv/insns/vwmulu_vx.h
+++ b/riscv/insns/vwmulu_vx.h
@@ -4,4 +4,3 @@ VI_VX_LOOP_WIDEN
 ({
   VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, *, +, uint);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwredsum_vs.h b/riscv/insns/vwredsum_vs.h
index 9563789..c7a87db 100644
--- a/riscv/insns/vwredsum_vs.h
+++ b/riscv/insns/vwredsum_vs.h
@@ -3,4 +3,3 @@ VI_VV_LOOP_WIDE_REDUCTION
 ({
   vd_0_res += vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwredsumu_vs.h b/riscv/insns/vwredsumu_vs.h
index 668f941..889a77d 100644
--- a/riscv/insns/vwredsumu_vs.h
+++ b/riscv/insns/vwredsumu_vs.h
@@ -3,4 +3,3 @@ VI_VV_ULOOP_WIDE_REDUCTION
 ({
   vd_0_res += vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwsmacc_vv.h b/riscv/insns/vwsmacc_vv.h
index 9a67068..86d588d 100644
--- a/riscv/insns/vwsmacc_vv.h
+++ b/riscv/insns/vwsmacc_vv.h
@@ -1,3 +1,2 @@
 // vwsmacc.vv vd, vs2, vs1
 VI_VVX_LOOP_WIDE_SSMA(vs1);
-VI_CHECK_1905
diff --git a/riscv/insns/vwsmacc_vx.h b/riscv/insns/vwsmacc_vx.h
index 69823a3..f0f04a3 100644
--- a/riscv/insns/vwsmacc_vx.h
+++ b/riscv/insns/vwsmacc_vx.h
@@ -1,3 +1,2 @@
 // vwsmacc.vx vd, vs2, rs1
 VI_VVX_LOOP_WIDE_SSMA(rs1);
-VI_CHECK_1905
diff --git a/riscv/insns/vwsmaccsu_vv.h b/riscv/insns/vwsmaccsu_vv.h
index cdebc7d..cf1aa1e 100644
--- a/riscv/insns/vwsmaccsu_vv.h
+++ b/riscv/insns/vwsmaccsu_vv.h
@@ -1,3 +1,2 @@
 // vwsmaccsu.vx vd, vs2, vs1
 VI_VVX_LOOP_WIDE_SU_SSMA(vs1);
-VI_CHECK_1905
diff --git a/riscv/insns/vwsmaccsu_vx.h b/riscv/insns/vwsmaccsu_vx.h
index d3379c7..681c309 100644
--- a/riscv/insns/vwsmaccsu_vx.h
+++ b/riscv/insns/vwsmaccsu_vx.h
@@ -1,3 +1,2 @@
 // vwsmaccsu.vx vd, vs2, rs1
 VI_VVX_LOOP_WIDE_SU_SSMA(rs1);
-VI_CHECK_1905
diff --git a/riscv/insns/vwsmaccu_vv.h b/riscv/insns/vwsmaccu_vv.h
index 8f767cf..e873d93 100644
--- a/riscv/insns/vwsmaccu_vv.h
+++ b/riscv/insns/vwsmaccu_vv.h
@@ -1,3 +1,2 @@
 // vwsmaccu.vv vd, vs2, vs1
 VI_VVX_LOOP_WIDE_USSMA(vs1);
-VI_CHECK_1905
diff --git a/riscv/insns/vwsmaccu_vx.h b/riscv/insns/vwsmaccu_vx.h
index 5227901..7318fa7 100644
--- a/riscv/insns/vwsmaccu_vx.h
+++ b/riscv/insns/vwsmaccu_vx.h
@@ -1,3 +1,2 @@
 // vwsmaccu vd, vs2, rs1
 VI_VVX_LOOP_WIDE_USSMA(rs1);
-VI_CHECK_1905
diff --git a/riscv/insns/vwsmaccus_vx.h b/riscv/insns/vwsmaccus_vx.h
index ed7608c..da1a1c8 100644
--- a/riscv/insns/vwsmaccus_vx.h
+++ b/riscv/insns/vwsmaccus_vx.h
@@ -1,3 +1,2 @@
 // vwsmaccus.vx  vd, vs2, rs1
 VI_VVX_LOOP_WIDE_US_SSMA(rs1);
-VI_CHECK_1905
diff --git a/riscv/insns/vwsub_vv.h b/riscv/insns/vwsub_vv.h
index 8df6660..99f9348 100644
--- a/riscv/insns/vwsub_vv.h
+++ b/riscv/insns/vwsub_vv.h
@@ -4,4 +4,3 @@ VI_VV_LOOP_WIDEN
 ({
   VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, -, +, int);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwsub_vx.h b/riscv/insns/vwsub_vx.h
index 33e98d6..affdf62 100644
--- a/riscv/insns/vwsub_vx.h
+++ b/riscv/insns/vwsub_vx.h
@@ -4,4 +4,3 @@ VI_VX_LOOP_WIDEN
 ({
   VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, -, +, int);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwsub_wv.h b/riscv/insns/vwsub_wv.h
index 5758341..10db730 100644
--- a/riscv/insns/vwsub_wv.h
+++ b/riscv/insns/vwsub_wv.h
@@ -4,4 +4,3 @@ VI_VV_LOOP_WIDEN
 ({
   VI_WIDE_WVX_OP(vs1, -, int);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwsub_wx.h b/riscv/insns/vwsub_wx.h
index 2a15c9a..f72341b 100644
--- a/riscv/insns/vwsub_wx.h
+++ b/riscv/insns/vwsub_wx.h
@@ -4,4 +4,3 @@ VI_VX_LOOP_WIDEN
 ({
   VI_WIDE_WVX_OP(rs1, -, int);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwsubu_vv.h b/riscv/insns/vwsubu_vv.h
index 9b72f65..cf68adb 100644
--- a/riscv/insns/vwsubu_vv.h
+++ b/riscv/insns/vwsubu_vv.h
@@ -4,4 +4,3 @@ VI_VV_LOOP_WIDEN
 ({
   VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, -, +, uint);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwsubu_vx.h b/riscv/insns/vwsubu_vx.h
index 86b6b50..3e972dd 100644
--- a/riscv/insns/vwsubu_vx.h
+++ b/riscv/insns/vwsubu_vx.h
@@ -4,4 +4,3 @@ VI_VX_LOOP_WIDEN
 ({
   VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, -, +, uint);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwsubu_wv.h b/riscv/insns/vwsubu_wv.h
index 553d3f8..3687c3d 100644
--- a/riscv/insns/vwsubu_wv.h
+++ b/riscv/insns/vwsubu_wv.h
@@ -4,4 +4,3 @@ VI_VV_LOOP_WIDEN
 ({
   VI_WIDE_WVX_OP(vs1, -, uint);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vwsubu_wx.h b/riscv/insns/vwsubu_wx.h
index 477dc7a..c7f20ed 100644
--- a/riscv/insns/vwsubu_wx.h
+++ b/riscv/insns/vwsubu_wx.h
@@ -4,4 +4,3 @@ VI_VX_LOOP_WIDEN
 ({
   VI_WIDE_WVX_OP(rs1, -, uint);
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vxor_vi.h b/riscv/insns/vxor_vi.h
index 7ef5ae9..b2dcf94 100644
--- a/riscv/insns/vxor_vi.h
+++ b/riscv/insns/vxor_vi.h
@@ -3,4 +3,3 @@ VI_VI_LOOP
 ({
   vd = simm5 ^ vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vxor_vv.h b/riscv/insns/vxor_vv.h
index 8a61d5e..c37b6ab 100644
--- a/riscv/insns/vxor_vv.h
+++ b/riscv/insns/vxor_vv.h
@@ -3,4 +3,3 @@ VI_VV_LOOP
 ({
   vd = vs1 ^ vs2;
 })
-VI_CHECK_1905
diff --git a/riscv/insns/vxor_vx.h b/riscv/insns/vxor_vx.h
index 8042ca3..8021e0e 100644
--- a/riscv/insns/vxor_vx.h
+++ b/riscv/insns/vxor_vx.h
@@ -3,4 +3,3 @@ VI_VX_LOOP
 ({
   vd = rs1 ^ vs2;
 })
-VI_CHECK_1905