WIP: move from gamma07 to gamma03

6 files changed, 177 insertions, 97 deletions

diff --git a/regression b/regression
index 99a4117..c885728 100755
--- a/regression
+++ b/regression
@@ -1,68 +1,134 @@
 #!/bin/bash
-where=$(dirname $(readlink -f "$0"))
-log_path=${where}/logs
+# Using SLURM to run the Spike regression
+# p
 
-slack_uri="https://hooks.slack.com/services/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"
+
+WORKSPACE=${HOME}/local
+BENGAL_TEAM_ROOT=${WORKSPACE}/bengal-team-regression
+set -x
+if [ -z -d "${BENGAL_TEAM_ROOT}" ]
+then
+  mkdir -p ${HOME}/local
+  pushd ${HOME}/local
+  git clone git@github.com:sifive/bengal-team.git bengal-team-regression
+  pushd bengal-team-regression
+  git submodule update --init --recursive
+  pushd riscv-isa-sim
+  git co rvv
+  popd 
+  pushd riscv-tests-internal
+  git co hankuan
+  popd
+  make -j
+else
+  pushd ${BENGAL_TEAM_ROOT}
+  make -j
+fi
+ASM="${BENGAL_TEAM_ROOT}/toolchain-prefix/bin/riscv64-unknown-elf-gcc"
+SPIKE="${BENGAL_TEAM_ROOT}/spike-prefix/build-spike/spike"
+TEST_FRAMEWORK="${BENGAL_TEAM_ROOT}/riscv-tests-internal/vector"
+
+cwd=$(dirname $(readlink -f "$0")) 
+
+if [ -z "${cwd}/regression.db" ]
+then
+  sqlite3 ${cwd}/regression.db "CREATE TABLE regression \
+    (inx INTEGER PRIMARY KEY AUTOINCREMENT, seed TEXT, \
+    exp_time DATETIME, status TEXT);"
+fi
+
+if [ -z -d "${cwd}/out" ]
+then
+  mkdir "${cwd}/out"
+fi
 
 runs=$1
 if [ -z $1 ];then
     runs=1
 fi
 
-pipeline_st=10
-for i in $(seq 0 ${pipeline_st}); do
-  if [ ! -d ${where}/build_${i} ]
-  then
-    mkdir ${where}/build_${i}
-  fi
-done
-
-proc=()
-pids=()
+function gen_job_file {
+    job_name=$2
+    job_file="$1/${job_name}.job"
+    echo "#!/bin/bash
+#SBATCH --job-name=${job_name}.job
+#SBATCH --output=${cwd}/out/${job_name}.out
+#SBATCH --error=${cwd}/out/${job_name}.err
+#SBATCH --time=$5
+#SBATCH --mem=$4
+#SBATCH --cpus-per-task=$3
+#SBATCH --partition=standard
+#SBATCH --mail-user=davewen@sifive.com
+pushd ${target} 
+$6
+popd
+" > ${job_file}
+}
 
 for i in $(seq 1 ${runs}); do
     while true; do
       SEED=$RANDOM
-      result=$(sqlite3 ~/regression.db "SELECT 1 FROM regression WHERE seed = \"${SEED}\" AND status = 'init'")
+      result=$(sqlite3 ${cwd}/regression.db "SELECT 1 FROM regression \
+        WHERE seed = \"${SEED}\" AND status = 'init'")
       if [[ -z $result ]];then
-        result=$(sqlite3 ~/regression.db "INSERT INTO regression(seed, exp_time, status) SELECT \"${SEED}\", datetime('now'), 'init' WHERE NOT EXISTS(SELECT 1 FROM regression WHERE seed = \"${SEED}\")")
+        result=$(sqlite3 ${cwd}/regression.db "INSERT INTO regression(seed, \
+          exp_time, status) SELECT \"${SEED}\", datetime('now'), \
+          'init' WHERE NOT EXISTS(SELECT 1 FROM regression \
+          WHERE seed = \"${SEED}\")")
         break
       fi
     done
-    target="build_$(( i % ${pipeline_st} ))"
-    rm -rf ${where}/${target}/*
-    pushd ${target} 
-      cmake_out=$(cmake ../ \
-                  -DCMAKE_ASM_COMPILER="$where/../../toolchain-prefix/bin/riscv64-unknown-elf-gcc" \
-                  -DSPIKE="$where/../../spike-prefix/build-spike/spike" \
-                  -DSEED=$SEED \
-                  -DBASE=64 --VLEN=512 --ELEN=64 --SLEN=128 \
-                  "$where")
-      make  -j20 > /dev/null
-      ctest --timeout 10 -Q -O ${log_path}/${SEED}.log &
-      proc[${i}]=$!
-      pids[$!]=${SEED}
-    popd
+    target="${cwd}/regression/build_${SEED}"
+    echo $target
 
-    if [ $(( i % ${pipeline_st})) == 0 ]
+    if [ -z -d ${target} ]
     then
-      for pid in ${proc[*]}; do
-        wait $pid
-        SEED=${pids[$pid]}
-        if grep -Fxq Failed ${log_path}/${SEED}.log
-        then
-          sqlite3 ~/regression.db "update regression set status=\"failed\" where seed = \"${SEED}\""
-          #curl -X POST --data-urlencode "payload={\"channel\": \"#spike-vector\", \"username\": \"webhookbot\", \"text\": \"!!THIS IS REAL!! Spike Vector regression fail on SEED ${SEED}.\", \"icon_emoji\": \":scream:\"}" ${slack_uri}
-        else
-          echo "Success"
-          sqlite3 ~/regression.db "update regression set status=\"successed\" where seed = \"${SEED}\""
-        fi
-        echo "Run ${i} finished"
-        if [[ $((${i} % 10000)) == 0 ]]; then
-          echo "PASS"
-            #curl -X POST --data-urlencode "payload={\"channel\": \"#spike-vector\", \"username\": \"webhookbot\", \"text\": \"Spike suvived after ${i} cases.\", \"icon_emoji\": \":100:\"}" ${slack_uri}
-        fi
-      done
-
+      mkdir -p ${target}
+    else
+      rm -rf ${target}/*
     fi
+    gen_job_file ${target} "${SEED}_conf" 1 12000 "0-00:10" "\
+              cmake -DCMAKE_ASM_COMPILER=\"${ASM}\" \
+              -DSPIKE=\"${SPIKE}\" \
+              -DSEED=${SEED} \
+              -DBASE=64 --VLEN=512 --ELEN=64 --SLEN=128 \
+              \"${TEST_FRAMEWORK}\""
+
+    conf_job_file=$job_file
+    gen_job_file ${target} "${SEED}_make" 20 12000 "0-00:20" " \
+      make -j20 > /dev/null \
+      "
+    make_job_file=$job_file
+
+    CONF=$(sbatch ${conf_job_file})
+    MAKE=$(sbatch --dependency=afterok:${CONF##* } ${make_job_file})
+
+    dep_chain=
+
+    vpat=("v[abcde]", "vf[abcdefghijkl]", "vfm", "vf[nopqr]", "vf[stuvwxyz]", \
+          "vl", "vs", "v[mn]", "v[opqr]", "v[tuvwxyz]")
+    for pat in ${vpat[*]}; do
+      f_name=${pat/[/}
+      gen_job_file ${target} "${SEED}_ctest_${fname/]//}" 1 12000 "0-00:15" " \
+      ctest --timeout 10 -R .*${pat}.* --ouput-log ${target}/${SEED}_${i}.log;
+      "
+      dep=$(sbatch --dependency=afterok:${MAKE##* } ${job_file})
+      dep_chain+=":${dep##* }"
+    done
+
+    gen_job_file ${target} "${SEED}_result" 1 1000 "0-00:01" " \
+      if grep -Fxq Failed ${target}/*.log \
+      then \
+        sqlite3 ${cwd}/regression.db "update regression set \
+        status=\"failed\" where seed = \"${SEED}\"" \
+        grep -Fxq Failed ${target}/*.log \
+      else \
+        sqlite3 ${cwd}/regression.db "update regression set \
+        status=\"successed\" where seed = \"${SEED}\"" \
+      fi \
+      #rm -rf ${target}
+    "
+
+    sbatch --dependency=afterany$dep_chain ${job_file}
+    break
 done
diff --git a/riscv/decode.h b/riscv/decode.h
index 0253003..7f32a68 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -23,6 +23,10 @@
 
 typedef int64_t sreg_t;
 typedef uint64_t reg_t;
+#ifndef __SIZEOF_INT128__
+typedef int __int128 __attribute__ ((__mode__ (TI)));
+typedef unsigned int __uint128 __attribute__ ((__mode__ (TI)));
+#endif
 typedef __int128 int128_t;
 typedef unsigned __int128 uint128_t;
 
@@ -1611,7 +1615,6 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
     memset(tail, 0, (P.VU.vlmax - vl) * ((P.VU.vsew >> 3) * 1)); \
   }\
   P.VU.vstart = 0; \
-  set_fp_exceptions;
 
 #define VI_VFP_LOOP_WIDE_END \
   } \
@@ -1634,13 +1637,13 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
   }
 
 #define VI_VFP_LOOP_CMP_END \
-    switch(P.VU.vsew) { \
-    case 32: { \
+  switch(P.VU.vsew) { \
+    case e32: { \
       vdi = (vdi & ~mmask) | (((res) << mpos) & mmask); \
       break; \
     } \
-    case 16: \
-    case 8: \
+    case e16: \
+    case e8: \
     default: \
       softfloat_exceptionFlags = 1; \
       break; \
@@ -1661,10 +1664,20 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
 
 #define VI_VFP_VV_LOOP(BODY) \
   VI_VFP_LOOP_BASE \
-  float32_t &vd = P.VU.elt<float32_t>(rd_num, i); \
-  float32_t vs1 = P.VU.elt<float32_t>(rs1_num, i); \
-  float32_t vs2 = P.VU.elt<float32_t>(rs2_num, i); \
-  BODY; \
+  switch(P.VU.vsew) { \
+    case e32: {\
+      float32_t &vd = P.VU.elt<float32_t>(rd_num, i); \
+      float32_t vs1 = P.VU.elt<float32_t>(rs1_num, i); \
+      float32_t vs2 = P.VU.elt<float32_t>(rs2_num, i); \
+      BODY; \
+      set_fp_exceptions; \
+      break; \
+    }\
+    case e16: \
+    case e8: \
+    default: \
+      require(0); \
+  }; \
   DEBUG_RVV_FP_VV; \
   VI_VFP_LOOP_END
 
@@ -1691,6 +1704,26 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
   DEBUG_RVV_FP_VF; \
   VI_VFP_LOOP_END
 
+#define VI_VFP_VF_LOOP2(BODY) \
+  VI_VFP_LOOP_BASE \
+  switch(P.VU.vsew) { \
+    case e32: {\
+      float32_t &vd = P.VU.elt<float32_t>(rd_num, i); \
+      float32_t rs1 = f32(READ_FREG(rs1_num)); \
+      float32_t vs2 = P.VU.elt<float32_t>(rs2_num, i); \
+      BODY; \
+      set_fp_exceptions; \
+      break; \
+    }\
+    case e16: \
+    case e8: \
+    default: \
+      require(0); \
+  }; \
+  DEBUG_RVV_FP_VF; \
+  VI_VFP_LOOP_END
+
+
 #define VI_VFP_LOOP_CMP(BODY) \
   VI_VFP_LOOP_CMP_BASE \
   BODY; \
@@ -1700,13 +1733,24 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
 #define VI_VFP_VF_LOOP_WIDE(BODY) \
   VI_VFP_LOOP_BASE \
   VI_CHECK_DSS(false); \
-  float64_t &vd = P.VU.elt<float64_t>(rd_num, i); \
-  float64_t vs2 = f32_to_f64(P.VU.elt<float32_t>(rs2_num, i)); \
-  float64_t rs1 = f32_to_f64(f32(READ_FREG(rs1_num))); \
-  BODY; \
+    switch(P.VU.vsew) { \
+    case e32: {\
+      float64_t &vd = P.VU.elt<float64_t>(rd_num, i); \
+      float64_t vs2 = f32_to_f64(P.VU.elt<float32_t>(rs2_num, i)); \
+      float64_t rs1 = f32_to_f64(f32(READ_FREG(rs1_num))); \
+      BODY; \
+      set_fp_exceptions; \
+      break; \
+    }\
+    case e16: \
+    case e8: \
+    default: \
+      require(0); \
+  }; \
   DEBUG_RVV_FP_VV; \
   VI_VFP_LOOP_WIDE_END
 
+
 #define VI_VFP_VV_LOOP_WIDE(BODY) \
   VI_VFP_LOOP_BASE \
   VI_CHECK_DSS(true); \
diff --git a/riscv/execute.cc b/riscv/execute.cc
index 8950ffa..480e80e 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -145,26 +145,11 @@ void processor_t::step(size_t n)
             state.single_step = state.STEP_STEPPED;
           }
 
-          if (debug && !state.prev_state) { // lazy init
-            prev_reg_state_t *saved = new prev_reg_state_t;
-            memcpy(&saved->VU, &VU, sizeof(vectorUnit_t));
-            int v_regfile_sz = NVPR * (VU.VLEN/8);
-            saved->VU.reg_file = malloc(v_regfile_sz);
-            for (int i=0; i<NXPR; ++i) (reg_t&)saved->XPR[i] = 0xdeadbeefcafebabe;
-            for (int i=0; i<NFPR; ++i) saved->FPR.write(i, freg(f64(161803398875)));
-            for (int i=0; i<NVPR; ++i) {
-              for (reg_t j=0; j<VU.VLEN/32; ++j) {
-                saved->VU.elt<uint32_t>(i, j) = f32(0xdeadbeef).v;
-              }
-            }
-            state.prev_state = saved;
-          }
-
           insn_fetch_t fetch = mmu->load_insn(pc);
           if (debug && !state.serialized)
             disasm(fetch.insn);
           pc = execute_insn(this, pc, fetch);
-
+#if 0
           if (debug && !state.serialized) {
             prev_reg_state_t *saved = state.prev_state;
             if (saved->VU.setvl_count != VU.setvl_count) {
@@ -209,7 +194,7 @@ void processor_t::step(size_t n)
               VU.reg_referenced[i] = 0;
             }
           }
-
+#endif
           advance_pc();
         }
       }
diff --git a/riscv/insns/vfadd_vf.h b/riscv/insns/vfadd_vf.h
index c85f208..02aeba9 100644
--- a/riscv/insns/vfadd_vf.h
+++ b/riscv/insns/vfadd_vf.h
@@ -1,13 +1,5 @@
 // vfadd.vf vd, vs2, rs1
-VI_VFP_VF_LOOP
+VI_VFP_VF_LOOP2
 ({
-  switch(P.VU.vsew) {
-  case e32:
     vd = f32_add(rs1, vs2);
-    break;
-  case e16:
-  case e8:
-  default:
-    softfloat_exceptionFlags = 1;
-  };
 })
diff --git a/riscv/insns/vfadd_vv.h b/riscv/insns/vfadd_vv.h
index 143f1af..de0ae53 100644
--- a/riscv/insns/vfadd_vv.h
+++ b/riscv/insns/vfadd_vv.h
@@ -1,13 +1,5 @@
 // vfadd.vv vd, vs2, vs1
 VI_VFP_VV_LOOP
 ({
-  switch(P.VU.vsew) {
-  case e32:
-    vd = f32_add(vs1, vs2);
-    break;
-  case e16:
-  case e8:
-  default:
-    softfloat_exceptionFlags = 1;
-  };
+  vd = f32_add(vs1, vs2);
 })
diff --git a/riscv/processor.h b/riscv/processor.h
index b284f11..7724851 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -165,7 +165,8 @@ class vectorUnit_t {
     // vector element for varies SEW
     template<class T>
       T& elt(reg_t vReg, reg_t n){
-        assert(vsew!=0);
+        assert(vsew != 0);
+        assert((VLEN >> 3)/sizeof(T) > 0);
         reg_t elts_per_reg = (VLEN >> 3) / (sizeof(T));
         vReg += n / elts_per_reg;
         n = n % elts_per_reg;