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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-05-16 19:21:47 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-05-16 19:21:47 -0700 |
| commit | 970959e4b096b07b5af94030b515180503123524 (patch) | |
| tree | 5fca419a047904f03aa8c858339e058be9ddc589 | |
| parent | 28229ac7f04e0ab0b2cb142782adbb656a84715d (diff) | |
| download | spike-970959e4b096b07b5af94030b515180503123524.zip spike-970959e4b096b07b5af94030b515180503123524.tar.gz spike-970959e4b096b07b5af94030b515180503123524.tar.bz2 | |
rvv: fix missng empty line
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/riscv.mk.in | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 5891aeb..98f7cdc 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -485,6 +485,7 @@ riscv_insn_ext_v_alu_int = \ vxor_vi \ vxor_vv \ vxor_vx \ + riscv_insn_ext_v_alu_fp = \ vfadd_vf \ vfadd_vv \ |