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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-10-29 01:53:30 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-10-29 01:53:30 -0700 |
| commit | 7c85cc44d13547ab7260438d97671d7f423e5d6c (patch) | |
| tree | da15b99ce9b267dfcc3242241be214c8c3a8c7d5 | |
| parent | 7eeee127dac2a0eb71f5b0ac4921af017070513c (diff) | |
| download | spike-7c85cc44d13547ab7260438d97671d7f423e5d6c.zip spike-7c85cc44d13547ab7260438d97671d7f423e5d6c.tar.gz spike-7c85cc44d13547ab7260438d97671d7f423e5d6c.tar.bz2 | |
rvv: fix marvelous vsetvlo again
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 3db6b54..74c5a2a 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -235,7 +235,7 @@ reg_t vectorUnit_t::set_vl(int regId, reg_t reqVL, reg_t newType){ if (vlmax == 0) { vl = 0; } else if (regId == 0) { - vl = vsew == old_sew && vlmul == old_lmul ? vl : 0; + vl = vl > vlmax ? vlmax : vl; } else if (regId == -1) { vl = vlmax; } else if (regId >= 0) { |