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| author | Dave.Wen <dave.wen@sifive.com> | 2019-06-03 02:27:06 -0700 |
|---|---|---|
| committer | Dave.Wen <dave.wen@sifive.com> | 2019-06-03 02:27:06 -0700 |
| commit | 3d734deab1223172a04ac9e98d23e1c9850cf923 (patch) | |
| tree | b7de2edb5ecd15381427ae64939db449298e7a4c | |
| parent | 82013cb42c092e71045226a4df3c5663a36de660 (diff) | |
| download | spike-3d734deab1223172a04ac9e98d23e1c9850cf923.zip spike-3d734deab1223172a04ac9e98d23e1c9850cf923.tar.gz spike-3d734deab1223172a04ac9e98d23e1c9850cf923.tar.bz2 | |
rvv: refactor to the VU
147 files changed, 602 insertions, 602 deletions
diff --git a/riscv/insns/csrrc.h b/riscv/insns/csrrc.h index bf01a87..a3c69cb 100644 --- a/riscv/insns/csrrc.h +++ b/riscv/insns/csrrc.h @@ -2,9 +2,9 @@ bool write = insn.rs1() != 0; int csr = validate_csr(insn.csr(), write); reg_t old; if (check_vcsr(csr)) { - old = p->VU.get_vcsr(csr); + old = P.VU.get_vcsr(csr); if (write) { - p->VU.set_vcsr(csr, old & ~RS1); + P.VU.set_vcsr(csr, old & ~RS1); } }else{ old = p->get_csr(csr); diff --git a/riscv/insns/csrrci.h b/riscv/insns/csrrci.h index 2ebb8c3..4308fc5 100644 --- a/riscv/insns/csrrci.h +++ b/riscv/insns/csrrci.h @@ -2,9 +2,9 @@ bool write = insn.rs1() != 0; int csr = validate_csr(insn.csr(), write); reg_t old; if (check_vcsr(csr)) { - old = p->VU.get_vcsr(csr); + old = P.VU.get_vcsr(csr); if (write) { - p->VU.set_vcsr(csr, old & ~(reg_t)insn.rs1()); + P.VU.set_vcsr(csr, old & ~(reg_t)insn.rs1()); } }else{ old = p->get_csr(csr); diff --git a/riscv/insns/csrrs.h b/riscv/insns/csrrs.h index 2e3c95d..f1fc7bf 100644 --- a/riscv/insns/csrrs.h +++ b/riscv/insns/csrrs.h @@ -2,9 +2,9 @@ bool write = insn.rs1() != 0; int csr = validate_csr(insn.csr(), write); reg_t old; if (check_vcsr(csr)) { - old = p->VU.get_vcsr(csr); + old = P.VU.get_vcsr(csr); if (write) { - p->VU.set_vcsr(csr, old | RS1); + P.VU.set_vcsr(csr, old | RS1); } }else{ old = p->get_csr(csr); diff --git a/riscv/insns/csrrsi.h b/riscv/insns/csrrsi.h index cbdc3a1..0ac071a 100644 --- a/riscv/insns/csrrsi.h +++ b/riscv/insns/csrrsi.h @@ -2,9 +2,9 @@ bool write = insn.rs1() != 0; int csr = validate_csr(insn.csr(), write); reg_t old; if (check_vcsr(csr)) { - old = p->VU.get_vcsr(csr); + old = P.VU.get_vcsr(csr); if (write) { - p->VU.set_vcsr(csr, old | insn.rs1()); + P.VU.set_vcsr(csr, old | insn.rs1()); } }else{ old = p->get_csr(csr); diff --git a/riscv/insns/csrrw.h b/riscv/insns/csrrw.h index f1e5780..09ece83 100644 --- a/riscv/insns/csrrw.h +++ b/riscv/insns/csrrw.h @@ -1,8 +1,8 @@ int csr = validate_csr(insn.csr(), true); reg_t old; if (check_vcsr(csr)) { - old = p->VU.get_vcsr(csr); - p->VU.set_vcsr(csr, RS1); + old = P.VU.get_vcsr(csr); + P.VU.set_vcsr(csr, RS1); }else{ old = p->get_csr(csr); p->set_csr(csr, RS1); diff --git a/riscv/insns/csrrwi.h b/riscv/insns/csrrwi.h index a3b4629..a2f4bab 100644 --- a/riscv/insns/csrrwi.h +++ b/riscv/insns/csrrwi.h @@ -1,8 +1,8 @@ int csr = validate_csr(insn.csr(), true); reg_t old; if (check_vcsr(csr)) { - old = p->VU.get_vcsr(csr); - p->VU.set_vcsr(csr, insn.rs1()); + old = P.VU.get_vcsr(csr); + P.VU.set_vcsr(csr, insn.rs1()); }else{ old = p->get_csr(csr); p->set_csr(csr, insn.rs1()); diff --git a/riscv/insns/vaadd_vi.h b/riscv/insns/vaadd_vi.h index 17c4c93..0b75aa5 100644 --- a/riscv/insns/vaadd_vi.h +++ b/riscv/insns/vaadd_vi.h @@ -1,5 +1,5 @@ // vaadd: Averaging adds of integers -VRM xrm = p->VU.get_vround_mode(); +VRM xrm = P.VU.get_vround_mode(); VI_VI_LOOP ({ int64_t result = vsext(simm5, sew) + vsext(vs2, sew); diff --git a/riscv/insns/vadc_vi.h b/riscv/insns/vadc_vi.h index a42ddc4..62fea00 100644 --- a/riscv/insns/vadc_vi.h +++ b/riscv/insns/vadc_vi.h @@ -1,6 +1,6 @@ // vadc.vi vd, vs2, simm5 require(insn.v_vm() == 1); -require(!(insn.rd() == 0 && p->VU.vlmul > 1)); +require(!(insn.rd() == 0 && P.VU.vlmul > 1)); VI_VI_LOOP ({ auto &v0 = P.VU.elt<uint64_t>(0, midx); diff --git a/riscv/insns/vadc_vv.h b/riscv/insns/vadc_vv.h index 535d017..5e85e45 100644 --- a/riscv/insns/vadc_vv.h +++ b/riscv/insns/vadc_vv.h @@ -1,6 +1,6 @@ // vadc.vv vd, vs2, rs1 require(insn.v_vm() == 1); -require(!(insn.rd() == 0 && p->VU.vlmul > 1)); +require(!(insn.rd() == 0 && P.VU.vlmul > 1)); VI_VV_LOOP ({ auto &v0 = P.VU.elt<uint64_t>(0, midx); diff --git a/riscv/insns/vadc_vx.h b/riscv/insns/vadc_vx.h index a3a17bf..59a1dff 100644 --- a/riscv/insns/vadc_vx.h +++ b/riscv/insns/vadc_vx.h @@ -1,6 +1,6 @@ // vadc.vx vd, vs2, rs1 require(insn.v_vm() == 1); -require(!(insn.rd() == 0 && p->VU.vlmul > 1)); +require(!(insn.rd() == 0 && P.VU.vlmul > 1)); VI_VX_LOOP ({ auto &v0 = P.VU.elt<uint64_t>(0, midx); diff --git a/riscv/insns/vcompress_vm.h b/riscv/insns/vcompress_vm.h index f4952c0..dbe67fd 100644 --- a/riscv/insns/vcompress_vm.h +++ b/riscv/insns/vcompress_vm.h @@ -1,19 +1,19 @@ // vcompress vd, vs2, vs1 -require(p->VU.vsew >= e8 && p->VU.vsew <= e64); -require(!p->VU.vill); -require(p->VU.vstart == 0); -reg_t sew = p->VU.vsew; -reg_t vl = p->VU.vl; +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); +require(!P.VU.vill); +require(P.VU.vstart == 0); +reg_t sew = P.VU.vsew; +reg_t vl = P.VU.vl; reg_t rd_num = insn.rd(); reg_t rs1_num = insn.rs1(); reg_t rs2_num = insn.rs2(); reg_t pos = 0; for (reg_t i = P.VU.vstart ; i < vl; ++i) { - const int mlen = p->VU.vmlen; + const int mlen = P.VU.vmlen; const int midx = (mlen * i) / 64; const int mpos = (mlen * i) % 64; - bool do_mask = (p->VU.elt<uint64_t>(rs1_num, midx) >> mpos) & 0x1; + bool do_mask = (P.VU.elt<uint64_t>(rs1_num, midx) >> mpos) & 0x1; if (do_mask) { switch (sew) { case e8: diff --git a/riscv/insns/vfadd_vf.h b/riscv/insns/vfadd_vf.h index d51dd2f..17a5e83 100644 --- a/riscv/insns/vfadd_vf.h +++ b/riscv/insns/vfadd_vf.h @@ -1,7 +1,7 @@ // vfadd.vf vd, vs2, rs1 VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_add(rs1, vs2); break; diff --git a/riscv/insns/vfadd_vv.h b/riscv/insns/vfadd_vv.h index a43c381..ed0a3ce 100644 --- a/riscv/insns/vfadd_vv.h +++ b/riscv/insns/vfadd_vv.h @@ -1,7 +1,7 @@ // vfadd.vv vd, vs2, vs1 VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_add(vs1, vs2); break; diff --git a/riscv/insns/vfdiv_vf.h b/riscv/insns/vfdiv_vf.h index 911c8ee..10362e9 100644 --- a/riscv/insns/vfdiv_vf.h +++ b/riscv/insns/vfdiv_vf.h @@ -1,7 +1,7 @@ // vfdiv.vf vd, vs2, rs1 VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_div(vs2, rs1); break; diff --git a/riscv/insns/vfdiv_vv.h b/riscv/insns/vfdiv_vv.h index d208c2d..28cffa1 100644 --- a/riscv/insns/vfdiv_vv.h +++ b/riscv/insns/vfdiv_vv.h @@ -1,7 +1,7 @@ // vfdiv.vv vd, vs2, vs1 VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_div(vs2, vs1); break; diff --git a/riscv/insns/vfdot_vv.h b/riscv/insns/vfdot_vv.h index 7539800..86241a2 100644 --- a/riscv/insns/vfdot_vv.h +++ b/riscv/insns/vfdot_vv.h @@ -1,7 +1,7 @@ // vfdot.vv vd, vs2, vs1 VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_add(vd, f32_mul(vs2, vs1)); break; diff --git a/riscv/insns/vfmacc_vf.h b/riscv/insns/vfmacc_vf.h index 4fc7272..417ae8a 100644 --- a/riscv/insns/vfmacc_vf.h +++ b/riscv/insns/vfmacc_vf.h @@ -1,7 +1,7 @@ // vfmacc.vf vd, rs1, vs2, vm # vd[i] = +(vs2[i] * x[rs1]) + vd[i] VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_mulAdd(rs1, vs2, vd); break; diff --git a/riscv/insns/vfmacc_vv.h b/riscv/insns/vfmacc_vv.h index eba6d09..b2218b6 100644 --- a/riscv/insns/vfmacc_vv.h +++ b/riscv/insns/vfmacc_vv.h @@ -1,7 +1,7 @@ // vfmacc.vv vd, rs1, vs2, vm # vd[i] = +(vs2[i] * vs1[i]) + vd[i] VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_mulAdd(vs1, vs2, vd); break; diff --git a/riscv/insns/vfmadd_vf.h b/riscv/insns/vfmadd_vf.h index 7a0aa06..6e3e761 100644 --- a/riscv/insns/vfmadd_vf.h +++ b/riscv/insns/vfmadd_vf.h @@ -1,7 +1,7 @@ // vfmadd: vd[i] = +(vd[i] * f[rs1]) + vs2[i] VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_mulAdd(vd, rs1, vs2); break; diff --git a/riscv/insns/vfmadd_vv.h b/riscv/insns/vfmadd_vv.h index af58602..501255e 100644 --- a/riscv/insns/vfmadd_vv.h +++ b/riscv/insns/vfmadd_vv.h @@ -1,7 +1,7 @@ // vfmadd: vd[i] = +(vd[i] * vs1[i]) + vs2[i] VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_mulAdd(vd, vs1, vs2); break; diff --git a/riscv/insns/vfmax_vf.h b/riscv/insns/vfmax_vf.h index a1f943c..cd3b621 100644 --- a/riscv/insns/vfmax_vf.h +++ b/riscv/insns/vfmax_vf.h @@ -1,7 +1,7 @@ // vfmax VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_max(vs2, rs1); break; diff --git a/riscv/insns/vfmax_vv.h b/riscv/insns/vfmax_vv.h index e438678..d0f79ef 100644 --- a/riscv/insns/vfmax_vv.h +++ b/riscv/insns/vfmax_vv.h @@ -1,7 +1,7 @@ // vfmax VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_max(vs2, vs1); break; diff --git a/riscv/insns/vfmin_vf.h b/riscv/insns/vfmin_vf.h index b565f7b..6d0a71f 100644 --- a/riscv/insns/vfmin_vf.h +++ b/riscv/insns/vfmin_vf.h @@ -1,7 +1,7 @@ // vfmin vd, vs2, rs1 VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_min(vs2, rs1); break; diff --git a/riscv/insns/vfmin_vv.h b/riscv/insns/vfmin_vv.h index d139bba..d7ac765 100644 --- a/riscv/insns/vfmin_vv.h +++ b/riscv/insns/vfmin_vv.h @@ -1,7 +1,7 @@ // vfmin vd, vs2, vs1 VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_min(vs2, vs1); break; diff --git a/riscv/insns/vfmsac_vf.h b/riscv/insns/vfmsac_vf.h index e65d535..bfe758a 100644 --- a/riscv/insns/vfmsac_vf.h +++ b/riscv/insns/vfmsac_vf.h @@ -1,7 +1,7 @@ // vfmsac: vd[i] = +(f[rs1] * vs2[i]) - vd[i] VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_mulAdd(rs1, vs2, f32(vd.v ^ F32_SIGN)); break; diff --git a/riscv/insns/vfmsac_vv.h b/riscv/insns/vfmsac_vv.h index c719600..8455f0c 100644 --- a/riscv/insns/vfmsac_vv.h +++ b/riscv/insns/vfmsac_vv.h @@ -1,7 +1,7 @@ // vfmsac: vd[i] = +(vs1[i] * vs2[i]) - vd[i] VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_mulAdd(vs1, vs2, f32(vd.v ^ F32_SIGN)); break; diff --git a/riscv/insns/vfmsub_vf.h b/riscv/insns/vfmsub_vf.h index 1794326..4567f6f 100644 --- a/riscv/insns/vfmsub_vf.h +++ b/riscv/insns/vfmsub_vf.h @@ -1,7 +1,7 @@ // vfmsub: vd[i] = +(vd[i] * f[rs1]) - vs2[i] VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_mulAdd(vd, rs1, f32(vs2.v ^ F32_SIGN)); break; diff --git a/riscv/insns/vfmsub_vv.h b/riscv/insns/vfmsub_vv.h index d75ff4c..b3c6137 100644 --- a/riscv/insns/vfmsub_vv.h +++ b/riscv/insns/vfmsub_vv.h @@ -1,7 +1,7 @@ // vfmsub: vd[i] = +(vd[i] * vs1[i]) - vs2[i] VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_mulAdd(vd, vs1, f32(vs2.v ^ F32_SIGN)); break; diff --git a/riscv/insns/vfmul_vf.h b/riscv/insns/vfmul_vf.h index 2d25db8..1e78af8 100644 --- a/riscv/insns/vfmul_vf.h +++ b/riscv/insns/vfmul_vf.h @@ -1,7 +1,7 @@ // vfmul.vf vd, vs2, rs1, vm VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_mul(vs2, rs1); break; diff --git a/riscv/insns/vfmul_vv.h b/riscv/insns/vfmul_vv.h index 2dd492f..3ec63b1 100644 --- a/riscv/insns/vfmul_vv.h +++ b/riscv/insns/vfmul_vv.h @@ -1,7 +1,7 @@ // vfmul.vv vd, vs1, vs2, vm VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_mul(vs1, vs2); break; diff --git a/riscv/insns/vfmv_f_s.h b/riscv/insns/vfmv_f_s.h index 714a03f..234b35c 100644 --- a/riscv/insns/vfmv_f_s.h +++ b/riscv/insns/vfmv_f_s.h @@ -1,23 +1,23 @@ // vfmv_f_s: rd = vs2[0] (rs1=0) require(insn.v_vm() == 1); require_fp; -require(p->VU.vsew == e8 || p->VU.vsew == e16 || p->VU.vsew == e32 || p->VU.vsew == e64); +require(P.VU.vsew == e8 || P.VU.vsew == e16 || P.VU.vsew == e32 || P.VU.vsew == e64); reg_t rs2_num = insn.rs2(); uint64_t vs2_0 = 0; -const reg_t sew = p->VU.vsew; +const reg_t sew = P.VU.vsew; switch(sew) { case e8: - vs2_0 = p->VU.elt<uint8_t>(rs2_num, 0); + vs2_0 = P.VU.elt<uint8_t>(rs2_num, 0); break; case e16: - vs2_0 = p->VU.elt<uint16_t>(rs2_num, 0); + vs2_0 = P.VU.elt<uint16_t>(rs2_num, 0); break; case e32: - vs2_0 = p->VU.elt<uint32_t>(rs2_num, 0); + vs2_0 = P.VU.elt<uint32_t>(rs2_num, 0); break; default: - vs2_0 = p->VU.elt<uint64_t>(rs2_num, 0); + vs2_0 = P.VU.elt<uint64_t>(rs2_num, 0); break; } diff --git a/riscv/insns/vfmv_s_f.h b/riscv/insns/vfmv_s_f.h index 677110b..303c920 100644 --- a/riscv/insns/vfmv_s_f.h +++ b/riscv/insns/vfmv_s_f.h @@ -1,23 +1,23 @@ // vfmv_s_f: vd[0] = rs1 (vs2=0) require(insn.v_vm() == 1); require_fp; -require(p->VU.vsew == e32); -reg_t vl = p->VU.vl; +require(P.VU.vsew == e32); +reg_t vl = P.VU.vl; if (vl > 0) { reg_t rd_num = insn.rd(); - reg_t sew = p->VU.vsew; + reg_t sew = P.VU.vsew; if (FLEN == 64) - p->VU.elt<uint32_t>(rd_num, 0) = f64(FRS1).v; + P.VU.elt<uint32_t>(rd_num, 0) = f64(FRS1).v; else - p->VU.elt<uint32_t>(rd_num, 0) = f32(FRS1).v; + P.VU.elt<uint32_t>(rd_num, 0) = f32(FRS1).v; - const reg_t max_len = p->VU.VLEN / sew; + const reg_t max_len = P.VU.VLEN / sew; for (reg_t i = 1; i < max_len; ++i){ switch(sew) { case e32: - p->VU.elt<uint32_t>(rd_num, i) = 0; + P.VU.elt<uint32_t>(rd_num, i) = 0; break; default: require(false); diff --git a/riscv/insns/vfnmacc_vf.h b/riscv/insns/vfnmacc_vf.h index e835a3d..9e45e2a 100644 --- a/riscv/insns/vfnmacc_vf.h +++ b/riscv/insns/vfnmacc_vf.h @@ -1,7 +1,7 @@ // vfnmacc: vd[i] = -(f[rs1] * vs2[i]) - vd[i] VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_mulAdd(rs1, f32(vs2.v ^ F32_SIGN), f32(vd.v ^ F32_SIGN)); break; diff --git a/riscv/insns/vfnmacc_vv.h b/riscv/insns/vfnmacc_vv.h index 7690d39..f6f07c3 100644 --- a/riscv/insns/vfnmacc_vv.h +++ b/riscv/insns/vfnmacc_vv.h @@ -1,7 +1,7 @@ // vfnmacc: vd[i] = -(vs1[i] * vs2[i]) - vd[i] VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_mulAdd(f32(vs2.v ^ F32_SIGN), vs1, f32(vd.v ^ F32_SIGN)); break; diff --git a/riscv/insns/vfnmadd_vf.h b/riscv/insns/vfnmadd_vf.h index 59d2ad1..9b456ef 100644 --- a/riscv/insns/vfnmadd_vf.h +++ b/riscv/insns/vfnmadd_vf.h @@ -1,7 +1,7 @@ // vfnmadd: vd[i] = -(vd[i] * f[rs1]) - vs2[i] VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_mulAdd(f32(vd.v ^ F32_SIGN), rs1, f32(vs2.v ^ F32_SIGN)); break; diff --git a/riscv/insns/vfnmadd_vv.h b/riscv/insns/vfnmadd_vv.h index 34aef81..f4aaede 100644 --- a/riscv/insns/vfnmadd_vv.h +++ b/riscv/insns/vfnmadd_vv.h @@ -1,7 +1,7 @@ // vfnmadd: vd[i] = -(vd[i] * vs1[i]) - vs2[i] VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_mulAdd(f32(vd.v ^ F32_SIGN), vs1, f32(vs2.v ^ F32_SIGN)); break; diff --git a/riscv/insns/vfnmsac_vf.h b/riscv/insns/vfnmsac_vf.h index c2aed33..5ab3da3 100644 --- a/riscv/insns/vfnmsac_vf.h +++ b/riscv/insns/vfnmsac_vf.h @@ -1,7 +1,7 @@ // vfnmsac: vd[i] = -(f[rs1] * vs2[i]) + vd[i] VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_mulAdd(rs1, f32(vs2.v ^ F32_SIGN), vd); break; diff --git a/riscv/insns/vfnmsac_vv.h b/riscv/insns/vfnmsac_vv.h index d190207..9abb653 100644 --- a/riscv/insns/vfnmsac_vv.h +++ b/riscv/insns/vfnmsac_vv.h @@ -1,7 +1,7 @@ // vfnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs2[i] * vs1[i]) + vd[i] VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_mulAdd(f32(vs1.v ^ F32_SIGN), vs2, vd); break; diff --git a/riscv/insns/vfnmsub_vf.h b/riscv/insns/vfnmsub_vf.h index baffcba..d7e8a3d 100644 --- a/riscv/insns/vfnmsub_vf.h +++ b/riscv/insns/vfnmsub_vf.h @@ -1,7 +1,7 @@ // vfnmsub: vd[i] = -(vd[i] * f[rs1]) + vs2[i] VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_mulAdd(f32(vd.v ^ F32_SIGN), rs1, vs2); break; diff --git a/riscv/insns/vfnmsub_vv.h b/riscv/insns/vfnmsub_vv.h index 20d5ca1..b11f541 100644 --- a/riscv/insns/vfnmsub_vv.h +++ b/riscv/insns/vfnmsub_vv.h @@ -1,7 +1,7 @@ // vfnmsub: vd[i] = -(vd[i] * vs1[i]) + vs2[i] VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_mulAdd(f32(vd.v ^ F32_SIGN), vs1, vs2); break; diff --git a/riscv/insns/vfsgnj_vf.h b/riscv/insns/vfsgnj_vf.h index 76ca896..b6f5ea1 100644 --- a/riscv/insns/vfsgnj_vf.h +++ b/riscv/insns/vfsgnj_vf.h @@ -1,7 +1,7 @@ // vfsgnj vd, vs2, vs1 VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = fsgnj32(rs1.v, vs2.v, false, false); break; diff --git a/riscv/insns/vfsgnj_vv.h b/riscv/insns/vfsgnj_vv.h index 8ada8dc..cc8487e 100644 --- a/riscv/insns/vfsgnj_vv.h +++ b/riscv/insns/vfsgnj_vv.h @@ -1,7 +1,7 @@ // vfsgnj VFP_VV_LOOP ({ - switch(p->VU.vsew) { + switch(P.VU.vsew) { case e32: vd = fsgnj32(vs1.v, vs2.v, false, false); break; diff --git a/riscv/insns/vfsgnjn_vf.h b/riscv/insns/vfsgnjn_vf.h index fad5552..b25037a 100644 --- a/riscv/insns/vfsgnjn_vf.h +++ b/riscv/insns/vfsgnjn_vf.h @@ -1,7 +1,7 @@ // vfsgnn VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = fsgnj32(rs1.v, vs2.v, true, false); break; diff --git a/riscv/insns/vfsgnjn_vv.h b/riscv/insns/vfsgnjn_vv.h index 41d0576..383eea7 100644 --- a/riscv/insns/vfsgnjn_vv.h +++ b/riscv/insns/vfsgnjn_vv.h @@ -1,7 +1,7 @@ // vfsgnn VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = fsgnj32(vs1.v, vs2.v, true, false); break; diff --git a/riscv/insns/vfsgnjx_vf.h b/riscv/insns/vfsgnjx_vf.h index e1b98a2..d39f22b 100644 --- a/riscv/insns/vfsgnjx_vf.h +++ b/riscv/insns/vfsgnjx_vf.h @@ -1,7 +1,7 @@ // vfsgnx VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = fsgnj32(rs1.v, vs2.v, false, true); break; diff --git a/riscv/insns/vfsgnjx_vv.h b/riscv/insns/vfsgnjx_vv.h index 2a522f0..c3f25dd 100644 --- a/riscv/insns/vfsgnjx_vv.h +++ b/riscv/insns/vfsgnjx_vv.h @@ -1,7 +1,7 @@ // vfsgnx VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = fsgnj32(vs1.v, vs2.v, false, true); break; diff --git a/riscv/insns/vfsub_vf.h b/riscv/insns/vfsub_vf.h index 87a9d6c..c95bf93 100644 --- a/riscv/insns/vfsub_vf.h +++ b/riscv/insns/vfsub_vf.h @@ -1,7 +1,7 @@ // vfsub.vf vd, vs2, rs1 VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_sub(vs2, rs1); break; diff --git a/riscv/insns/vfsub_vv.h b/riscv/insns/vfsub_vv.h index 8f7e42e..eefbb3b 100644 --- a/riscv/insns/vfsub_vv.h +++ b/riscv/insns/vfsub_vv.h @@ -1,7 +1,7 @@ // vfsub.vv vd, vs2, vs1 VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f32_sub(vs2, vs1); break; diff --git a/riscv/insns/vfunary0_vv.h b/riscv/insns/vfunary0_vv.h index 0f6d11b..4872b9c 100644 --- a/riscv/insns/vfunary0_vv.h +++ b/riscv/insns/vfunary0_vv.h @@ -11,74 +11,74 @@ case VFUNARY0::VFWCVT_F_F_V: VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: //cvt switch (rs1_num) { case VFUNARY0::VFCVT_XU_F_V: - p->VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, STATE.frm, true); + P.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, STATE.frm, true); break; case VFUNARY0::VFCVT_X_F_V: - p->VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, STATE.frm, true); + P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, STATE.frm, true); break; case VFUNARY0::VFCVT_F_XU_V: { - auto vs2_u = p->VU.elt<uint32_t>(rs2_num, i); + auto vs2_u = P.VU.elt<uint32_t>(rs2_num, i); vd = ui32_to_f32(vs2_u); break; } case VFUNARY0::VFCVT_F_X_V: { - auto vs2_i = p->VU.elt<int32_t>(rs2_num, i); + auto vs2_i = P.VU.elt<int32_t>(rs2_num, i); vd = i32_to_f32(vs2_i); break; } //wcvt case VFUNARY0::VFWCVT_XU_F_V: - p->VU.elt<uint64_t>(rd_num, i) = f32_to_ui64(vs2, STATE.frm, true); + P.VU.elt<uint64_t>(rd_num, i) = f32_to_ui64(vs2, STATE.frm, true); break; case VFUNARY0::VFWCVT_X_F_V: - p->VU.elt<int64_t>(rd_num, i) = f32_to_i64(vs2, STATE.frm, true); + P.VU.elt<int64_t>(rd_num, i) = f32_to_i64(vs2, STATE.frm, true); break; case VFUNARY0::VFWCVT_F_XU_V: { - auto vs2_u = p->VU.elt<uint32_t>(rs2_num, i); - p->VU.elt<float64_t>(rd_num, i) = ui32_to_f64(vs2_u); + auto vs2_u = P.VU.elt<uint32_t>(rs2_num, i); + P.VU.elt<float64_t>(rd_num, i) = ui32_to_f64(vs2_u); break; } case VFUNARY0::VFWCVT_F_X_V: { - auto vs2_i = p->VU.elt<int32_t>(rs2_num, i); - p->VU.elt<float64_t>(rd_num, i) = i32_to_f64(vs2_i); + auto vs2_i = P.VU.elt<int32_t>(rs2_num, i); + P.VU.elt<float64_t>(rd_num, i) = i32_to_f64(vs2_i); break; } case VFUNARY0::VFWCVT_F_F_V: { - auto vs2_f = p->VU.elt<float32_t>(rs2_num, i); - p->VU.elt<float64_t>(rd_num, i) = f32_to_f64(vs2_f); + auto vs2_f = P.VU.elt<float32_t>(rs2_num, i); + P.VU.elt<float64_t>(rd_num, i) = f32_to_f64(vs2_f); break; } //ncvt case VFUNARY0::VFNCVT_XU_F_V: { - auto vs2_d = p->VU.elt<float64_t>(rs2_num, i); - p->VU.elt<uint32_t>(rd_num, i) = f64_to_ui32(vs2_d, STATE.frm, true); + auto vs2_d = P.VU.elt<float64_t>(rs2_num, i); + P.VU.elt<uint32_t>(rd_num, i) = f64_to_ui32(vs2_d, STATE.frm, true); break; } case VFUNARY0::VFNCVT_X_F_V: { - auto vs2_d = p->VU.elt<float64_t>(rs2_num, i); - p->VU.elt<int32_t>(rd_num, i) = f64_to_i32(vs2_d, STATE.frm, true); + auto vs2_d = P.VU.elt<float64_t>(rs2_num, i); + P.VU.elt<int32_t>(rd_num, i) = f64_to_i32(vs2_d, STATE.frm, true); break; } case VFUNARY0::VFNCVT_F_XU_V: { - auto vs2_u = p->VU.elt<uint64_t>(rs2_num, i); + auto vs2_u = P.VU.elt<uint64_t>(rs2_num, i); vd = ui64_to_f32(vs2_u); break; } case VFUNARY0::VFNCVT_F_X_V: { - auto vs2_i = p->VU.elt<int64_t>(rs2_num, i); + auto vs2_i = P.VU.elt<int64_t>(rs2_num, i); vd = i64_to_f32(vs2_i); break; } case VFUNARY0::VFNCVT_F_F_V: - auto vs2_d = p->VU.elt<float64_t>(rs2_num, i); - p->VU.elt<float32_t>(rd_num, i) = f64_to_f32(vs2_d); + auto vs2_d = P.VU.elt<float64_t>(rs2_num, i); + P.VU.elt<float32_t>(rd_num, i) = f64_to_f32(vs2_d); break; } break; diff --git a/riscv/insns/vfunary1_vv.h b/riscv/insns/vfunary1_vv.h index 66344fc..0388f00 100644 --- a/riscv/insns/vfunary1_vv.h +++ b/riscv/insns/vfunary1_vv.h @@ -1,7 +1,7 @@ // VFUNARY1 encoding space VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: if (rs1_num == VFUNARY1::VFSQRT_V) { vd = f32_sqrt(vs2); diff --git a/riscv/insns/vfwadd_vf.h b/riscv/insns/vfwadd_vf.h index d12453d..6db61c1 100644 --- a/riscv/insns/vfwadd_vf.h +++ b/riscv/insns/vfwadd_vf.h @@ -1,7 +1,7 @@ // vfwadd.vf vd, vs2, rs1 VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: P.VU.elt<float64_t>(rd_num, i) = f64_add(f32_to_f64(vs2), f32_to_f64(rs1)); break; diff --git a/riscv/insns/vfwadd_vv.h b/riscv/insns/vfwadd_vv.h index e230067..b797ec5 100644 --- a/riscv/insns/vfwadd_vv.h +++ b/riscv/insns/vfwadd_vv.h @@ -1,7 +1,7 @@ // vfwadd.vv vd, vs2, vs1 VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: P.VU.elt<float64_t>(rd_num, i) = f64_add(f32_to_f64(vs2), f32_to_f64(vs1)); break; diff --git a/riscv/insns/vfwadd_wf.h b/riscv/insns/vfwadd_wf.h index e9b8061..fbfaec8 100644 --- a/riscv/insns/vfwadd_wf.h +++ b/riscv/insns/vfwadd_wf.h @@ -1,7 +1,7 @@ // vfwadd.wf vd, vs2, vs1 VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: P.VU.elt<float64_t>(rd_num, i) = f64_add(P.VU.elt<float64_t>(rs2_num, i), f32_to_f64(rs1)); diff --git a/riscv/insns/vfwadd_wv.h b/riscv/insns/vfwadd_wv.h index 1bdd9b9..cf48ae2 100644 --- a/riscv/insns/vfwadd_wv.h +++ b/riscv/insns/vfwadd_wv.h @@ -1,7 +1,7 @@ // vfwadd.wv vd, vs2, vs1 VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: P.VU.elt<float64_t>(rd_num, i) = f64_add(P.VU.elt<float64_t>(rs2_num, i), f32_to_f64(vs1)); diff --git a/riscv/insns/vfwmacc_vf.h b/riscv/insns/vfwmacc_vf.h index ff928e7..71cc582 100644 --- a/riscv/insns/vfwmacc_vf.h +++ b/riscv/insns/vfwmacc_vf.h @@ -1,7 +1,7 @@ // vfwmacc.vf vd, vs2, rs1 VFP_VVF_LOOP_WIDE ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f64_mulAdd(rs1, vs2, vd); break; diff --git a/riscv/insns/vfwmacc_vv.h b/riscv/insns/vfwmacc_vv.h index 287a867..b57e9dd 100644 --- a/riscv/insns/vfwmacc_vv.h +++ b/riscv/insns/vfwmacc_vv.h @@ -1,7 +1,7 @@ // vfwmacc.vv vd, vs2, vs1 VFP_VVF_LOOP_WIDE ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f64_mulAdd(vs1, vs2, vd); break; diff --git a/riscv/insns/vfwmsac_vf.h b/riscv/insns/vfwmsac_vf.h index 8da3844..84f7618 100644 --- a/riscv/insns/vfwmsac_vf.h +++ b/riscv/insns/vfwmsac_vf.h @@ -1,7 +1,7 @@ // vfwmsac.vf vd, vs2, rs1 VFP_VVF_LOOP_WIDE ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f64_mulAdd(rs1, vs2, f64(vd.v ^ F64_SIGN)); break; diff --git a/riscv/insns/vfwmsac_vv.h b/riscv/insns/vfwmsac_vv.h index 03dcaf9..056a597 100644 --- a/riscv/insns/vfwmsac_vv.h +++ b/riscv/insns/vfwmsac_vv.h @@ -1,7 +1,7 @@ // vfwmsac.vv vd, vs2, vs1 VFP_VVF_LOOP_WIDE ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f64_mulAdd(vs1, vs2, f64(vd.v ^ F64_SIGN)); break; diff --git a/riscv/insns/vfwmul_vf.h b/riscv/insns/vfwmul_vf.h index e33bc21..18d2241 100644 --- a/riscv/insns/vfwmul_vf.h +++ b/riscv/insns/vfwmul_vf.h @@ -1,7 +1,7 @@ // vfwmul.vf vd, vs2, rs1 VFP_VVF_LOOP_WIDE ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f64_add(vs2, rs1); break; diff --git a/riscv/insns/vfwmul_vv.h b/riscv/insns/vfwmul_vv.h index a6e68dd..2c58aff 100644 --- a/riscv/insns/vfwmul_vv.h +++ b/riscv/insns/vfwmul_vv.h @@ -1,7 +1,7 @@ // vfwmul.vv vd, vs2, vs1 VFP_VVF_LOOP_WIDE ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f64_add(vs2, vs1); break; diff --git a/riscv/insns/vfwnmacc_vf.h b/riscv/insns/vfwnmacc_vf.h index 9850209..79ddf8a 100644 --- a/riscv/insns/vfwnmacc_vf.h +++ b/riscv/insns/vfwnmacc_vf.h @@ -1,7 +1,7 @@ // vfwnmacc.vf vd, vs2, rs1 VFP_VVF_LOOP_WIDE ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f64_mulAdd(f64(rs1.v ^ F64_SIGN), vs2, vd); break; diff --git a/riscv/insns/vfwnmacc_vv.h b/riscv/insns/vfwnmacc_vv.h index ffdb5da..bc89d57 100644 --- a/riscv/insns/vfwnmacc_vv.h +++ b/riscv/insns/vfwnmacc_vv.h @@ -1,7 +1,7 @@ // vfwnmacc.vv vd, vs2, vs1 VFP_VVF_LOOP_WIDE ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f64_mulAdd(f64(vs1.v ^ F64_SIGN), vs2, vd); break; diff --git a/riscv/insns/vfwnmsac_vf.h b/riscv/insns/vfwnmsac_vf.h index e28af1d..1db0e56 100644 --- a/riscv/insns/vfwnmsac_vf.h +++ b/riscv/insns/vfwnmsac_vf.h @@ -1,7 +1,7 @@ // vfwnmacc.vf vd, vs2, rs1 VFP_VVF_LOOP_WIDE ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f64_mulAdd(f64(rs1.v ^ F64_SIGN), vs2, f64(vd.v ^ F64_SIGN)); diff --git a/riscv/insns/vfwnmsac_vv.h b/riscv/insns/vfwnmsac_vv.h index d078476..1323928 100644 --- a/riscv/insns/vfwnmsac_vv.h +++ b/riscv/insns/vfwnmsac_vv.h @@ -1,7 +1,7 @@ // vfwnmsac.vv vd, vs2, vs1 VFP_VVF_LOOP_WIDE ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: vd = f64_mulAdd(f64(vs1.v ^ F64_SIGN), vs2, f64(vd.v ^ F64_SIGN)); diff --git a/riscv/insns/vfwsub_vf.h b/riscv/insns/vfwsub_vf.h index fc6a9c4..9c4dd4d 100644 --- a/riscv/insns/vfwsub_vf.h +++ b/riscv/insns/vfwsub_vf.h @@ -1,7 +1,7 @@ // vfwsub.vf vd, vs2, rs1 VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: P.VU.elt<float64_t>(rd_num, i) = f64_sub(f32_to_f64(vs2), f32_to_f64(rs1)); break; diff --git a/riscv/insns/vfwsub_vv.h b/riscv/insns/vfwsub_vv.h index b32a904..d86a512 100644 --- a/riscv/insns/vfwsub_vv.h +++ b/riscv/insns/vfwsub_vv.h @@ -1,7 +1,7 @@ // vfwsub.vv vd, vs2, vs1 VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: P.VU.elt<float64_t>(rd_num, i) = f64_sub(f32_to_f64(vs2), f32_to_f64(vs1)); break; diff --git a/riscv/insns/vfwsub_wf.h b/riscv/insns/vfwsub_wf.h index 43ab741..f6f4e26 100644 --- a/riscv/insns/vfwsub_wf.h +++ b/riscv/insns/vfwsub_wf.h @@ -1,7 +1,7 @@ // vfwsub.wf vd, vs2, rs1 VFP_VF_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: P.VU.elt<float64_t>(rd_num, i) = f64_sub(P.VU.elt<float64_t>(rs2_num, i), f32_to_f64(rs1)); diff --git a/riscv/insns/vfwsub_wv.h b/riscv/insns/vfwsub_wv.h index 6525cf4..14df9be 100644 --- a/riscv/insns/vfwsub_wv.h +++ b/riscv/insns/vfwsub_wv.h @@ -1,7 +1,7 @@ // vfwsub.wv vd, vs2, vs1 VFP_VV_LOOP ({ - switch(p->VU.vsew){ + switch(P.VU.vsew){ case e32: P.VU.elt<float64_t>(rd_num, i) = f64_sub(P.VU.elt<float64_t>(rs2_num, i), f32_to_f64(vs1)); diff --git a/riscv/insns/vid_v.h b/riscv/insns/vid_v.h index 8bd531e..8e71304 100644 --- a/riscv/insns/vid_v.h +++ b/riscv/insns/vid_v.h @@ -1,8 +1,8 @@ // vmpopc rd, vs2, vm -require(p->VU.vsew >= e8 && p->VU.vsew <= e64); -require(!p->VU.vill); -reg_t vl = p->VU.vl; -reg_t sew = p->VU.vsew; +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); +require(!P.VU.vill); +reg_t vl = P.VU.vl; +reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); reg_t rs1_num = insn.rs1(); reg_t rs2_num = insn.rs2(); diff --git a/riscv/insns/vlb_v.h b/riscv/insns/vlb_v.h index b255d18..3ca4b38 100644 --- a/riscv/insns/vlb_v.h +++ b/riscv/insns/vlb_v.h @@ -1,28 +1,28 @@ // vlb.v and vlseg[2-8]b.v -require(p->VU.vsew >= e8); +require(P.VU.vsew >= e8); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; STRIP(i) V_ELEMENT_SKIP(i); for (reg_t fn = 0; fn < nf; ++fn) { int64_t val = MMU.load_int8(baseAddr + (i * nf + fn) * 1); - if (p->VU.vsew == e8) { - p->VU.elt<uint8_t>(vd + fn, vreg_inx) = is_valid ? val : 0; - } else if (p->VU.vsew == e16) { - p->VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? val : 0; - } else if (p->VU.vsew == e32) { - p->VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + if (P.VU.vsew == e8) { + P.VU.elt<uint8_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + } else if (P.VU.vsew == e16) { + P.VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + } else if (P.VU.vsew == e32) { + P.VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } else { - p->VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + P.VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vlbu_v.h b/riscv/insns/vlbu_v.h index 4b79f73..a33bd38 100644 --- a/riscv/insns/vlbu_v.h +++ b/riscv/insns/vlbu_v.h @@ -1,28 +1,28 @@ // vlbu.v and vlseg[2-8]bu.v -require(p->VU.vsew >= e8); +require(P.VU.vsew >= e8); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; V_ELEMENT_SKIP(i); STRIP(i) for (reg_t fn = 0; fn < nf; ++fn) { uint64_t val = MMU.load_uint8(baseAddr + (i *nf + fn) * 1); - if (p->VU.vsew == e8) { - p->VU.elt<uint8_t>(vd + fn, vreg_inx) = is_valid ? val : 0; - } else if (p->VU.vsew == e16) { - p->VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? val : 0; - } else if (p->VU.vsew == e32) { - p->VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + if (P.VU.vsew == e8) { + P.VU.elt<uint8_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + } else if (P.VU.vsew == e16) { + P.VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + } else if (P.VU.vsew == e32) { + P.VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } else { - p->VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + P.VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vle_v.h b/riscv/insns/vle_v.h index 864ca7d..4767f92 100644 --- a/riscv/insns/vle_v.h +++ b/riscv/insns/vle_v.h @@ -1,13 +1,13 @@ // vle.v and vlseg[2-8]e.v -const reg_t sew = p->VU.vsew; +const reg_t sew = P.VU.vsew; const reg_t nf = insn.v_nf() + 1; -const reg_t vl = p->VU.vl; +const reg_t vl = P.VU.vl; const reg_t elt_byte = sew / 8; require(sew >= e8 && sew <= e64); -require((nf * p->VU.vlmul) <= (NVPR / 4)); +require((nf * P.VU.vlmul) <= (NVPR / 4)); reg_t baseAddr = RS1; reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; STRIP(i) @@ -15,19 +15,19 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { switch (sew) { case e8: - p->VU.elt<uint8_t>(vd + fn, vreg_inx) = is_valid ? + P.VU.elt<uint8_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int8(baseAddr + (i * nf + fn) * elt_byte) : 0; break; case e16: - p->VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? + P.VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int16(baseAddr + (i * nf + fn) * elt_byte) : 0; break; case e32: - p->VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? + P.VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int32(baseAddr + (i * nf + fn) * elt_byte) : 0; break; case e64: - p->VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? + P.VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int64(baseAddr + (i * nf + fn) * elt_byte) : 0; break; } @@ -35,5 +35,5 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vleff_v.h b/riscv/insns/vleff_v.h index bc89e9a..d3c4807 100644 --- a/riscv/insns/vleff_v.h +++ b/riscv/insns/vleff_v.h @@ -1,8 +1,8 @@ -require(p->VU.vsew >= e8 && p->VU.vsew <= e64); +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); const reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -const reg_t sew = p->VU.vsew; -const reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +const reg_t sew = P.VU.vsew; +const reg_t vl = P.VU.vl; const reg_t baseAddr = RS1; const reg_t rd_num = insn.rd(); bool early_stop = false; @@ -17,29 +17,29 @@ for (reg_t i = 0; i < P.VU.vlmax && vl != 0; ++i) { switch (sew) { case e8: - p->VU.elt<uint8_t>(rd_num + fn, vreg_inx) = + P.VU.elt<uint8_t>(rd_num + fn, vreg_inx) = is_valid ? MMU.load_uint8(baseAddr + (i * nf + fn) * 1) : 0; - is_zero = is_valid && p->VU.elt<uint8_t>(rd_num + fn, vreg_inx) == 0; + is_zero = is_valid && P.VU.elt<uint8_t>(rd_num + fn, vreg_inx) == 0; break; case e16: - p->VU.elt<uint16_t>(rd_num + fn, vreg_inx) = + P.VU.elt<uint16_t>(rd_num + fn, vreg_inx) = is_valid ? MMU.load_uint16(baseAddr + (i * nf + fn) * 2) : 0; - is_zero = is_valid && p->VU.elt<uint16_t>(rd_num + fn, vreg_inx) == 0; + is_zero = is_valid && P.VU.elt<uint16_t>(rd_num + fn, vreg_inx) == 0; break; case e32: - p->VU.elt<uint32_t>(rd_num + fn, vreg_inx) = + P.VU.elt<uint32_t>(rd_num + fn, vreg_inx) = is_valid ? MMU.load_uint32(baseAddr + (i * nf + fn) * 4) : 0; - is_zero = is_valid && p->VU.elt<uint32_t>(rd_num + fn, vreg_inx) == 0; + is_zero = is_valid && P.VU.elt<uint32_t>(rd_num + fn, vreg_inx) == 0; break; case e64: - p->VU.elt<uint64_t>(rd_num + fn, vreg_inx) = + P.VU.elt<uint64_t>(rd_num + fn, vreg_inx) = is_valid ? MMU.load_uint64(baseAddr + (i * nf + fn) * 8) : 0; - is_zero = is_valid && p->VU.elt<uint64_t>(rd_num + fn, vreg_inx) == 0; + is_zero = is_valid && P.VU.elt<uint64_t>(rd_num + fn, vreg_inx) == 0; break; } if (is_zero) { - p->VU.vl = i; + P.VU.vl = i; early_stop = true; break; } @@ -50,5 +50,5 @@ for (reg_t i = 0; i < P.VU.vlmax && vl != 0; ++i) { } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vlh_v.h b/riscv/insns/vlh_v.h index eead12e..f866ea6 100644 --- a/riscv/insns/vlh_v.h +++ b/riscv/insns/vlh_v.h @@ -1,26 +1,26 @@ // vlh.v and vlseg[2-8]h.v -require(p->VU.vsew >= e16); +require(P.VU.vsew >= e16); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; V_ELEMENT_SKIP(i); STRIP(i) for (reg_t fn=0; fn<nf; ++fn) { int64_t val = MMU.load_int16(baseAddr + (i * nf + fn) * 2); - if (p->VU.vsew == e16) { - p->VU.elt<uint16_t>(vd+fn, vreg_inx) = is_valid ? val : 0; - } else if (p->VU.vsew == e32) { - p->VU.elt<uint32_t>(vd+fn, vreg_inx) = is_valid ? val : 0; + if (P.VU.vsew == e16) { + P.VU.elt<uint16_t>(vd+fn, vreg_inx) = is_valid ? val : 0; + } else if (P.VU.vsew == e32) { + P.VU.elt<uint32_t>(vd+fn, vreg_inx) = is_valid ? val : 0; } else { - p->VU.elt<uint64_t>(vd+fn, vreg_inx) = is_valid ? val : 0; + P.VU.elt<uint64_t>(vd+fn, vreg_inx) = is_valid ? val : 0; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vlhu_v.h b/riscv/insns/vlhu_v.h index 32a9039..9814e97 100644 --- a/riscv/insns/vlhu_v.h +++ b/riscv/insns/vlhu_v.h @@ -1,26 +1,26 @@ // vlhu.v and vlseg[2-8]hu.v -require(p->VU.vsew >= e16); +require(P.VU.vsew >= e16); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; V_ELEMENT_SKIP(i); STRIP(i) for (reg_t fn = 0; fn < nf; ++fn) { uint64_t val = MMU.load_uint16(baseAddr + (i * nf + fn) * 2); - if (p->VU.vsew == e16) { - p->VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? val : 0; - } else if (p->VU.vsew == e32) { - p->VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + if (P.VU.vsew == e16) { + P.VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + } else if (P.VU.vsew == e32) { + P.VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } else { - p->VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + P.VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vlsb_v.h b/riscv/insns/vlsb_v.h index c6bdd8d..15335df 100644 --- a/riscv/insns/vlsb_v.h +++ b/riscv/insns/vlsb_v.h @@ -1,29 +1,29 @@ // vlsb.v and vlsseg[2-8]b.v -require(p->VU.vsew >= e8); +require(P.VU.vsew >= e8); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = RS2; reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; STRIP(i) V_ELEMENT_SKIP(i); for (reg_t fn = 0; fn < nf; ++fn) { int64_t val = MMU.load_int8(baseAddr + i * stride + fn * 1); - if (p->VU.vsew == e8) { - p->VU.elt<uint8_t>(vd + fn, vreg_inx) = is_valid ? val : 0; - } else if (p->VU.vsew == e16) { - p->VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? val : 0; - } else if (p->VU.vsew == e32) { - p->VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + if (P.VU.vsew == e8) { + P.VU.elt<uint8_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + } else if (P.VU.vsew == e16) { + P.VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + } else if (P.VU.vsew == e32) { + P.VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } else { - p->VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + P.VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vlsbu_v.h b/riscv/insns/vlsbu_v.h index fa7e1d6..5c7227f 100644 --- a/riscv/insns/vlsbu_v.h +++ b/riscv/insns/vlsbu_v.h @@ -1,12 +1,12 @@ // vlsb.v and vlsseg[2-8]b.v -require(p->VU.vsew >= e8); +require(P.VU.vsew >= e8); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = RS2; reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; V_ELEMENT_SKIP(i); @@ -14,17 +14,17 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { uint64_t val = MMU.load_uint8(baseAddr + i * stride + fn * 1); - if (p->VU.vsew == e8) { - p->VU.elt<uint8_t>(vd + fn, vreg_inx) = is_valid ? val : 0; - } else if (p->VU.vsew == e16) { - p->VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? val : 0; - } else if (p->VU.vsew == e32) { - p->VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + if (P.VU.vsew == e8) { + P.VU.elt<uint8_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + } else if (P.VU.vsew == e16) { + P.VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + } else if (P.VU.vsew == e32) { + P.VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } else { - p->VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + P.VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vlse_v.h b/riscv/insns/vlse_v.h index 5532ccc..3fba383 100644 --- a/riscv/insns/vlse_v.h +++ b/riscv/insns/vlse_v.h @@ -1,14 +1,14 @@ // vlse.v and vlsseg[2-8]e.v -const reg_t sew = p->VU.vsew; +const reg_t sew = P.VU.vsew; require(sew >= e8 && sew <= e64); const reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -const reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +const reg_t vl = P.VU.vl; const reg_t elt_byte = sew / 8; reg_t baseAddr = RS1; reg_t stride = RS2; reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; V_ELEMENT_SKIP(i); @@ -16,24 +16,24 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { switch (sew) { case e8: - p->VU.elt<uint8_t>(vd + fn, vreg_inx) = is_valid ? + P.VU.elt<uint8_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int8(baseAddr + i * stride + fn * elt_byte) : 0; break; case e16: - p->VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? + P.VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int16(baseAddr + i * stride + fn * elt_byte) : 0; break; case e32: - p->VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? + P.VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int32(baseAddr + i * stride + fn * elt_byte) : 0; break; case e64: - p->VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? + P.VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int64(baseAddr + i * stride + fn * elt_byte) : 0; break; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vlsh_v.h b/riscv/insns/vlsh_v.h index c3de3f9..be864e3 100644 --- a/riscv/insns/vlsh_v.h +++ b/riscv/insns/vlsh_v.h @@ -1,28 +1,28 @@ // vlsh.v and vlsseg[2-8]h.v -require(p->VU.vsew >= e16); +require(P.VU.vsew >= e16); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = RS2; reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; STRIP(i) V_ELEMENT_SKIP(i); for (reg_t fn = 0; fn < nf; ++fn) { int64_t val = MMU.load_int16(baseAddr + i * stride + fn * 2); - if (p->VU.vsew == e16) { - p->VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? val : 0; - } else if (p->VU.vsew == e32) { - p->VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + if (P.VU.vsew == e16) { + P.VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + } else if (P.VU.vsew == e32) { + P.VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } else { - p->VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + P.VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vlshu_v.h b/riscv/insns/vlshu_v.h index 62d5bed..53e7755 100644 --- a/riscv/insns/vlshu_v.h +++ b/riscv/insns/vlshu_v.h @@ -1,27 +1,27 @@ // vlsh.v and vlsseg[2-8]h.v -require(p->VU.vsew >= e16); +require(P.VU.vsew >= e16); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = RS2; reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; V_ELEMENT_SKIP(i); STRIP(i) for (reg_t fn = 0; fn < nf; ++fn) { uint64_t val = MMU.load_uint16(baseAddr + i * stride + fn * 2); - if (p->VU.vsew == e16) { - p->VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? val : 0; - } else if (p->VU.vsew == e32) { - p->VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + if (P.VU.vsew == e16) { + P.VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + } else if (P.VU.vsew == e32) { + P.VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } else { - p->VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + P.VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vlsw_v.h b/riscv/insns/vlsw_v.h index 7e5df19..fa639b9 100644 --- a/riscv/insns/vlsw_v.h +++ b/riscv/insns/vlsw_v.h @@ -1,12 +1,12 @@ // vlsw.v and vlsseg[2-8]w.v -require(p->VU.vsew >= e32); +require(P.VU.vsew >= e32); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = RS2; reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; V_ELEMENT_SKIP(i); @@ -14,13 +14,13 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { int64_t val = MMU.load_int32(baseAddr + i * stride + fn * 4); - if (p->VU.vsew == e32) { - p->VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + if (P.VU.vsew == e32) { + P.VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } else { - p->VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + P.VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vlswu_v.h b/riscv/insns/vlswu_v.h index 9eab736..694d404 100644 --- a/riscv/insns/vlswu_v.h +++ b/riscv/insns/vlswu_v.h @@ -1,12 +1,12 @@ // vlsw.v and vlsseg[2-8]w.v -require(p->VU.vsew >= e32); +require(P.VU.vsew >= e32); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = RS2; reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; V_ELEMENT_SKIP(i); @@ -14,12 +14,12 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { uint64_t val = MMU.load_uint32(baseAddr + i * stride + fn * 4); - if (p->VU.vsew == e32) { - p->VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + if (P.VU.vsew == e32) { + P.VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } else { - p->VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + P.VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vlw_v.h b/riscv/insns/vlw_v.h index 02033b6..d9c4a39 100644 --- a/riscv/insns/vlw_v.h +++ b/riscv/insns/vlw_v.h @@ -1,11 +1,11 @@ // vlw.v and vlseg[2-8]w.v -require(p->VU.vsew >= e32); +require(P.VU.vsew >= e32); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; V_ELEMENT_SKIP(i); @@ -13,15 +13,15 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { int64_t val = MMU.load_int32(baseAddr + (i * nf + fn) * 4); - if (p->VU.vsew == e32) { - p->VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + if (P.VU.vsew == e32) { + P.VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } else { - p->VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + P.VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; if (nf >= 2) { VI_CHECK_1905; } diff --git a/riscv/insns/vlwu_v.h b/riscv/insns/vlwu_v.h index afaeede..2d3b19a 100644 --- a/riscv/insns/vlwu_v.h +++ b/riscv/insns/vlwu_v.h @@ -1,11 +1,11 @@ // vlwu.v and vlseg[2-8]wu.v -require(p->VU.vsew >= e32); +require(P.VU.vsew >= e32); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; V_ELEMENT_SKIP(i); @@ -13,13 +13,13 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { uint64_t val = MMU.load_uint32(baseAddr + (i * nf + fn) * 4); - if (p->VU.vsew == e32) { - p->VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + if (P.VU.vsew == e32) { + P.VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } else { - p->VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; + P.VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? val : 0; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vlxb_v.h b/riscv/insns/vlxb_v.h index 46d4ee0..aeabbdf 100644 --- a/riscv/insns/vlxb_v.h +++ b/riscv/insns/vlxb_v.h @@ -1,12 +1,12 @@ // vlxb.v and vlsseg[2-8]b.v -require(p->VU.vsew >= e8); +require(P.VU.vsew >= e8); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; DUPLICATE_VREG(stride, vlmax); for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; @@ -14,22 +14,22 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { STRIP(i) for (reg_t fn = 0; fn < nf; ++fn) { - switch (p->VU.vsew) { + switch (P.VU.vsew) { case e8: - p->VU.elt<uint8_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int8(baseAddr + index[i] + fn * 1) : 0; + P.VU.elt<uint8_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int8(baseAddr + index[i] + fn * 1) : 0; break; case e16: - p->VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int8(baseAddr + index[i] + fn * 1) : 0; + P.VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int8(baseAddr + index[i] + fn * 1) : 0; break; case e32: - p->VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int8(baseAddr + index[i] + fn * 1) : 0; + P.VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int8(baseAddr + index[i] + fn * 1) : 0; break; case e64: - p->VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int8(baseAddr + index[i] + fn * 1) : 0; + P.VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int8(baseAddr + index[i] + fn * 1) : 0; break; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vlxbu_v.h b/riscv/insns/vlxbu_v.h index d6f1a85..0f14c14 100644 --- a/riscv/insns/vlxbu_v.h +++ b/riscv/insns/vlxbu_v.h @@ -1,12 +1,12 @@ // vlxbu.v and vlxseg[2-8]bu.v -require(p->VU.vsew >= e8); +require(P.VU.vsew >= e8); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; DUPLICATE_VREG(stride, vlmax); for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; @@ -14,22 +14,22 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { STRIP(i) for (reg_t fn = 0; fn < nf; ++fn) { - switch (p->VU.vsew) { + switch (P.VU.vsew) { case e8: - p->VU.elt<uint8_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_uint8(baseAddr + index[i] + fn * 1) : 0; + P.VU.elt<uint8_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_uint8(baseAddr + index[i] + fn * 1) : 0; break; case e16: - p->VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_uint8(baseAddr + index[i] + fn * 1) : 0; + P.VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_uint8(baseAddr + index[i] + fn * 1) : 0; break; case e32: - p->VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_uint8(baseAddr + index[i] + fn * 1) : 0; + P.VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_uint8(baseAddr + index[i] + fn * 1) : 0; break; case e64: - p->VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_uint8(baseAddr + index[i] + fn * 1) : 0; + P.VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_uint8(baseAddr + index[i] + fn * 1) : 0; break; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vlxe_v.h b/riscv/insns/vlxe_v.h index ee32dfc..793eacb 100644 --- a/riscv/insns/vlxe_v.h +++ b/riscv/insns/vlxe_v.h @@ -1,14 +1,14 @@ // vlxe.v and vlxseg[2-8]e.v -const reg_t sew = p->VU.vsew; +const reg_t sew = P.VU.vsew; const reg_t nf = insn.v_nf() + 1; -const reg_t vl = p->VU.vl; +const reg_t vl = P.VU.vl; const reg_t elt_byte = sew / 8; require(sew >= e8 && sew <= e64); -require((nf * p->VU.vlmul) <= (NVPR / 4)); +require((nf * P.VU.vlmul) <= (NVPR / 4)); reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; DUPLICATE_VREG(stride, vlmax); for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; @@ -18,24 +18,24 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { switch (sew) { case e8: - p->VU.elt<uint8_t>(vd + fn, vreg_inx) = is_valid ? + P.VU.elt<uint8_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int8(baseAddr + index[i] + fn * elt_byte) : 0; break; case e16: - p->VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? + P.VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int16(baseAddr + index[i] + fn * elt_byte) : 0; break; case e32: - p->VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? + P.VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int32(baseAddr + index[i] + fn * elt_byte) : 0; break; case e64: - p->VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? + P.VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int64(baseAddr + index[i] + fn * elt_byte) : 0; break; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vlxh_v.h b/riscv/insns/vlxh_v.h index b81fc6e..96746b7 100644 --- a/riscv/insns/vlxh_v.h +++ b/riscv/insns/vlxh_v.h @@ -1,12 +1,12 @@ // vlxh.v and vlxseg[2-8]h.v -require(p->VU.vsew >= e16); +require(P.VU.vsew >= e16); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; DUPLICATE_VREG(stride, vlmax); for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; @@ -14,15 +14,15 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { STRIP(i) for (reg_t fn = 0; fn < nf; ++fn) { - switch (p->VU.vsew) { + switch (P.VU.vsew) { case e16: - p->VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int16(baseAddr + index[i] + fn * 2) : 0; + P.VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int16(baseAddr + index[i] + fn * 2) : 0; break; case e32: - p->VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int16(baseAddr + index[i] + fn * 2) : 0; + P.VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int16(baseAddr + index[i] + fn * 2) : 0; break; case e64: - p->VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int16(baseAddr + index[i] + fn * 2) : 0; + P.VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int16(baseAddr + index[i] + fn * 2) : 0; break; } } diff --git a/riscv/insns/vlxhu_v.h b/riscv/insns/vlxhu_v.h index 0bf3549..977de48 100644 --- a/riscv/insns/vlxhu_v.h +++ b/riscv/insns/vlxhu_v.h @@ -1,12 +1,12 @@ // vlxh.v and vlxseg[2-8]h.v -require(p->VU.vsew >= e16); +require(P.VU.vsew >= e16); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; DUPLICATE_VREG(stride, vlmax); for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; @@ -14,19 +14,19 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { STRIP(i) for (reg_t fn = 0; fn < nf; ++fn) { - switch (p->VU.vsew) { + switch (P.VU.vsew) { case e16: - p->VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_uint16(baseAddr + index[i] + fn * 2) : 0; + P.VU.elt<uint16_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_uint16(baseAddr + index[i] + fn * 2) : 0; break; case e32: - p->VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_uint16(baseAddr + index[i] + fn * 2) : 0; + P.VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_uint16(baseAddr + index[i] + fn * 2) : 0; break; case e64: - p->VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_uint16(baseAddr + index[i] + fn * 2) : 0; + P.VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_uint16(baseAddr + index[i] + fn * 2) : 0; break; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vlxw_v.h b/riscv/insns/vlxw_v.h index 26f6cb3..eb6e777 100644 --- a/riscv/insns/vlxw_v.h +++ b/riscv/insns/vlxw_v.h @@ -1,12 +1,12 @@ // vlxw.v and vlxseg[2-8]w.v -require(p->VU.vsew >= e32); +require(P.VU.vsew >= e32); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; DUPLICATE_VREG(stride, vlmax); for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; @@ -14,16 +14,16 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { STRIP(i) for (reg_t fn = 0; fn < nf; ++fn) { - switch (p->VU.vsew) { + switch (P.VU.vsew) { case e32: - p->VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int32(baseAddr + index[i] + fn * 4) : 0; + P.VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int32(baseAddr + index[i] + fn * 4) : 0; break; case e64: - p->VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int32(baseAddr + index[i] + fn * 4) : 0; + P.VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_int32(baseAddr + index[i] + fn * 4) : 0; break; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vlxwu_v.h b/riscv/insns/vlxwu_v.h index 0010fd6..d31cf60 100644 --- a/riscv/insns/vlxwu_v.h +++ b/riscv/insns/vlxwu_v.h @@ -1,12 +1,12 @@ // vlxwu.v and vlxseg[2-8]wu.v -require(p->VU.vsew >= e32); +require(P.VU.vsew >= e32); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vd = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; DUPLICATE_VREG(stride, vlmax); for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; @@ -14,16 +14,16 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { STRIP(i) for (reg_t fn = 0; fn < nf; ++fn) { - switch (p->VU.vsew) { + switch (P.VU.vsew) { case e32: - p->VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_uint32(baseAddr + index[i] + fn * 4) : 0; + P.VU.elt<uint32_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_uint32(baseAddr + index[i] + fn * 4) : 0; break; case e64: - p->VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_uint32(baseAddr + index[i] + fn * 4) : 0; + P.VU.elt<uint64_t>(vd + fn, vreg_inx) = is_valid ? MMU.load_uint32(baseAddr + index[i] + fn * 4) : 0; break; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vmerge_vi.h b/riscv/insns/vmerge_vi.h index e5089aa..6a29324 100644 --- a/riscv/insns/vmerge_vi.h +++ b/riscv/insns/vmerge_vi.h @@ -5,9 +5,9 @@ bool use_first = false; VI_VVXI_MERGE_LOOP ({ if (insn.v_vm() == 0) { - int midx = (p->VU.vmlen * i) / 32; - int mpos = (p->VU.vmlen * i) % 32; - do_mask = (p->VU.elt<uint32_t>(0, midx) >> mpos) & 0x1; + int midx = (P.VU.vmlen * i) / 32; + int mpos = (P.VU.vmlen * i) % 32; + do_mask = (P.VU.elt<uint32_t>(0, midx) >> mpos) & 0x1; } use_first = (insn.v_vm() == 1) || do_mask; diff --git a/riscv/insns/vmerge_vv.h b/riscv/insns/vmerge_vv.h index 96a211a..cf6b012 100644 --- a/riscv/insns/vmerge_vv.h +++ b/riscv/insns/vmerge_vv.h @@ -8,9 +8,9 @@ VI_VVXI_MERGE_LOOP use_first = false; if (insn.v_vm() == 0) { - int midx = (p->VU.vmlen * i) / 32; - int mpos = (p->VU.vmlen * i) % 32; - do_mask = (p->VU.elt<uint32_t>(0, midx) >> mpos) & 0x1; + int midx = (P.VU.vmlen * i) / 32; + int mpos = (P.VU.vmlen * i) % 32; + do_mask = (P.VU.elt<uint32_t>(0, midx) >> mpos) & 0x1; } use_first = (insn.v_vm() == 1) || do_mask; diff --git a/riscv/insns/vmerge_vx.h b/riscv/insns/vmerge_vx.h index 0b6c60d..b67204d 100644 --- a/riscv/insns/vmerge_vx.h +++ b/riscv/insns/vmerge_vx.h @@ -5,9 +5,9 @@ bool use_first = false; VI_VVXI_MERGE_LOOP ({ if (insn.v_vm() == 0) { - int midx = (p->VU.vmlen * i) / 32; - int mpos = (p->VU.vmlen * i) % 32; - do_mask = (p->VU.elt<uint32_t>(0, midx) >> mpos) & 0x1; + int midx = (P.VU.vmlen * i) / 32; + int mpos = (P.VU.vmlen * i) % 32; + do_mask = (P.VU.elt<uint32_t>(0, midx) >> mpos) & 0x1; } use_first = (insn.v_vm() == 1) || do_mask; diff --git a/riscv/insns/vmfirst_m.h b/riscv/insns/vmfirst_m.h index 0baa935..3198fe6 100644 --- a/riscv/insns/vmfirst_m.h +++ b/riscv/insns/vmfirst_m.h @@ -1,21 +1,21 @@ // vmfirst rd, vs2 -require(p->VU.vsew >= e8 && p->VU.vsew <= e64); -require(!p->VU.vill); -reg_t vl = p->VU.vl; -reg_t sew = p->VU.vsew; +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); +require(!P.VU.vill); +reg_t vl = P.VU.vl; +reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); reg_t rs2_num = insn.rs2(); -require(p->VU.vstart == 0); +require(P.VU.vstart == 0); reg_t pos = -1; -for (reg_t i=p->VU.vstart; i < vl; ++i){ +for (reg_t i=P.VU.vstart; i < vl; ++i){ V_LOOP_ELEMENT_SKIP - bool vs2_lsb = ((p->VU.elt<uint64_t>(rs2_num, midx ) >> mpos) & 0x1) == 1; + bool vs2_lsb = ((P.VU.elt<uint64_t>(rs2_num, midx ) >> mpos) & 0x1) == 1; if (vs2_lsb) { pos = i; break; } } -p->VU.vstart = 0; +P.VU.vstart = 0; WRITE_RD(pos); VI_CHECK_1905 diff --git a/riscv/insns/vmiota_m.h b/riscv/insns/vmiota_m.h index 9b6ca3d..75baaf3 100644 --- a/riscv/insns/vmiota_m.h +++ b/riscv/insns/vmiota_m.h @@ -1,21 +1,21 @@ // vmpopc rd, vs2, vm -require(p->VU.vsew >= e8 && p->VU.vsew <= e64); -require(!p->VU.vill); -reg_t vl = p->VU.vl; -reg_t sew = p->VU.vsew; +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); +require(!P.VU.vill); +reg_t vl = P.VU.vl; +reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); reg_t rs1_num = insn.rs1(); reg_t rs2_num = insn.rs2(); -require(p->VU.vstart == 0); +require(P.VU.vstart == 0); int cnt = 0; for (reg_t i = 0; i < vl; ++i) { - const int mlen = p->VU.vmlen; + const int mlen = P.VU.vmlen; const int midx = (mlen * i) / 64; const int mpos = (mlen * i) % 64; - bool vs2_lsb = ((p->VU.elt<uint64_t>(rs2_num, midx) >> mpos) & 0x1) == 1; - bool do_mask = (p->VU.elt<uint64_t>(0, midx) >> mpos) & 0x1; + bool vs2_lsb = ((P.VU.elt<uint64_t>(rs2_num, midx) >> mpos) & 0x1) == 1; + bool do_mask = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1; bool has_one = false; if (insn.v_vm() == 1 || (insn.v_vm() == 0 && do_mask)) { diff --git a/riscv/insns/vmpopc_m.h b/riscv/insns/vmpopc_m.h index af60dbc..7ea8499 100644 --- a/riscv/insns/vmpopc_m.h +++ b/riscv/insns/vmpopc_m.h @@ -1,25 +1,25 @@ // vmpopc rd, vs2, vm -require(p->VU.vsew >= e8 && p->VU.vsew <= e64); -require(!p->VU.vill); -reg_t vl = p->VU.vl; -reg_t sew = p->VU.vsew; +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); +require(!P.VU.vill); +reg_t vl = P.VU.vl; +reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); reg_t rs2_num = insn.rs2(); -require(p->VU.vstart == 0); +require(P.VU.vstart == 0); reg_t popcount = 0; -for (reg_t i=p->VU.vstart; i<vl; ++i){ - const int mlen = p->VU.vmlen; +for (reg_t i=P.VU.vstart; i<vl; ++i){ + const int mlen = P.VU.vmlen; const int midx = (mlen * i) / 32; const int mpos = (mlen * i) % 32; - bool vs2_lsb = ((p->VU.elt<uint32_t>(rs2_num, midx ) >> mpos) & 0x1) == 1; + bool vs2_lsb = ((P.VU.elt<uint32_t>(rs2_num, midx ) >> mpos) & 0x1) == 1; if (insn.v_vm() == 1) { popcount += vs2_lsb; } else { - bool do_mask = (p->VU.elt<uint32_t>(0, midx) >> mpos) & 0x1; + bool do_mask = (P.VU.elt<uint32_t>(0, midx) >> mpos) & 0x1; popcount += (vs2_lsb && do_mask); } } -p->VU.vstart = 0; +P.VU.vstart = 0; WRITE_RD(popcount); VI_CHECK_1905 diff --git a/riscv/insns/vmsbf_m.h b/riscv/insns/vmsbf_m.h index 38077fa..626e0d6 100644 --- a/riscv/insns/vmsbf_m.h +++ b/riscv/insns/vmsbf_m.h @@ -1,21 +1,21 @@ // vmsbf.m vd, vs2, vm -require(p->VU.vsew >= e8 && p->VU.vsew <= e64); -require(!p->VU.vill); -reg_t vl = p->VU.vl; -reg_t sew = p->VU.vsew; +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); +require(!P.VU.vill); +reg_t vl = P.VU.vl; +reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); reg_t rs1_num = insn.rs1(); reg_t rs2_num = insn.rs2(); bool has_one = false; for (reg_t i = P.VU.vstart; i < vl; ++i) { - const int mlen = p->VU.vmlen; + const int mlen = P.VU.vmlen; const int midx = (mlen * i) / 64; const int mpos = (mlen * i) % 64; const uint64_t mmask = (UINT64_MAX << (64 - mlen)) >> (64 - mlen - mpos); - bool vs2_lsb = ((p->VU.elt<uint64_t>(rs2_num, midx) >> mpos) & 0x1) == 1; - bool do_mask = (p->VU.elt<uint64_t>(0, midx) >> mpos) & 0x1; + bool vs2_lsb = ((P.VU.elt<uint64_t>(rs2_num, midx) >> mpos) & 0x1) == 1; + bool do_mask = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1; auto &vd = P.VU.elt<uint64_t>(rd_num, midx); @@ -31,5 +31,5 @@ for (reg_t i = P.VU.vstart; i < vl; ++i) { } VI_TAIL_ZERO_MASK(rd_num); -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vmsif_m.h b/riscv/insns/vmsif_m.h index 3e814ba..e4c8172 100644 --- a/riscv/insns/vmsif_m.h +++ b/riscv/insns/vmsif_m.h @@ -1,21 +1,21 @@ // vmpopc rd, vs2, vm -require(p->VU.vsew >= e8 && p->VU.vsew <= e64); -require(!p->VU.vill); -reg_t vl = p->VU.vl; -reg_t sew = p->VU.vsew; +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); +require(!P.VU.vill); +reg_t vl = P.VU.vl; +reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); reg_t rs1_num = insn.rs1(); reg_t rs2_num = insn.rs2(); bool has_one = false; for (reg_t i = P.VU.vstart ; i < vl; ++i) { - const int mlen = p->VU.vmlen; + const int mlen = P.VU.vmlen; const int midx = (mlen * i) / 64; const int mpos = (mlen * i) % 64; const uint64_t mmask = (UINT64_MAX << (64 - mlen)) >> (64 - mlen - mpos); - bool vs2_lsb = ((p->VU.elt<uint64_t>(rs2_num, midx ) >> mpos) & 0x1) == 1; - bool do_mask = (p->VU.elt<uint64_t>(0, midx) >> mpos) & 0x1; + bool vs2_lsb = ((P.VU.elt<uint64_t>(rs2_num, midx ) >> mpos) & 0x1) == 1; + bool do_mask = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1; auto &vd = P.VU.elt<uint64_t>(rd_num, midx); if (insn.v_vm() == 1 || (insn.v_vm() == 0 && do_mask)) { @@ -31,5 +31,5 @@ for (reg_t i = P.VU.vstart ; i < vl; ++i) { } VI_TAIL_ZERO_MASK(rd_num); -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vmsof_m.h b/riscv/insns/vmsof_m.h index 6bb5493..c5a8536 100644 --- a/riscv/insns/vmsof_m.h +++ b/riscv/insns/vmsof_m.h @@ -1,21 +1,21 @@ // vmsof.m rd, vs2, vm -require(p->VU.vsew >= e8 && p->VU.vsew <= e64); -require(!p->VU.vill); -reg_t vl = p->VU.vl; -reg_t sew = p->VU.vsew; +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); +require(!P.VU.vill); +reg_t vl = P.VU.vl; +reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); reg_t rs1_num = insn.rs1(); reg_t rs2_num = insn.rs2(); bool has_one = false; for (reg_t i = P.VU.vstart ; i < vl; ++i) { - const int mlen = p->VU.vmlen; + const int mlen = P.VU.vmlen; const int midx = (mlen * i) / 64; const int mpos = (mlen * i) % 64; const uint64_t mmask = (UINT64_MAX << (64 - mlen)) >> (64 - mlen - mpos); - bool vs2_lsb = ((p->VU.elt<uint64_t>(rs2_num, midx ) >> mpos) & 0x1) == 1; - bool do_mask = (p->VU.elt<uint64_t>(0, midx) >> mpos) & 0x1; + bool vs2_lsb = ((P.VU.elt<uint64_t>(rs2_num, midx ) >> mpos) & 0x1) == 1; + bool do_mask = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1; uint64_t &vd = P.VU.elt<uint64_t>(rd_num, midx); if (insn.v_vm() == 1 || (insn.v_vm() == 0 && do_mask)) { @@ -29,5 +29,5 @@ for (reg_t i = P.VU.vstart ; i < vl; ++i) { } VI_TAIL_ZERO_MASK(rd_num); -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vmv_s_x.h b/riscv/insns/vmv_s_x.h index 9026a91..76345cb 100644 --- a/riscv/insns/vmv_s_x.h +++ b/riscv/insns/vmv_s_x.h @@ -1,42 +1,42 @@ // vmv_s_x: vd[0] = rs1 require(insn.v_vm() == 1); -require(p->VU.vsew == e8 || p->VU.vsew == e16 || - p->VU.vsew == e32 || p->VU.vsew == e64); -reg_t vl = p->VU.vl; +require(P.VU.vsew == e8 || P.VU.vsew == e16 || + P.VU.vsew == e32 || P.VU.vsew == e64); +reg_t vl = P.VU.vl; if (vl > 0) { reg_t rd_num = insn.rd(); - reg_t sew = p->VU.vsew; + reg_t sew = P.VU.vsew; switch(sew) { case e8: - p->VU.elt<uint8_t>(rd_num, 0) = RS1; + P.VU.elt<uint8_t>(rd_num, 0) = RS1; break; case e16: - p->VU.elt<uint16_t>(rd_num, 0) = RS1; + P.VU.elt<uint16_t>(rd_num, 0) = RS1; break; case e32: - p->VU.elt<uint32_t>(rd_num, 0) = RS1; + P.VU.elt<uint32_t>(rd_num, 0) = RS1; break; default: - p->VU.elt<uint64_t>(rd_num, 0) = RS1; + P.VU.elt<uint64_t>(rd_num, 0) = RS1; break; } - const reg_t max_len = p->VU.VLEN / sew; + const reg_t max_len = P.VU.VLEN / sew; for (reg_t i = 1; i < max_len; ++i){ switch(sew) { case e8: - p->VU.elt<uint8_t>(rd_num, i) = 0; + P.VU.elt<uint8_t>(rd_num, i) = 0; break; case e16: - p->VU.elt<uint16_t>(rd_num, i) = 0; + P.VU.elt<uint16_t>(rd_num, i) = 0; break; case e32: - p->VU.elt<uint32_t>(rd_num, i) = 0; + P.VU.elt<uint32_t>(rd_num, i) = 0; break; default: - p->VU.elt<uint64_t>(rd_num, i) = 0; + P.VU.elt<uint64_t>(rd_num, i) = 0; break; } } diff --git a/riscv/insns/vnclip_vi.h b/riscv/insns/vnclip_vi.h index 1b23772..a7f448e 100644 --- a/riscv/insns/vnclip_vi.h +++ b/riscv/insns/vnclip_vi.h @@ -1,7 +1,7 @@ // vnclip: vd[i] = clip(round(vs2[i] + rnd) >> simm) -VRM xrm = p->VU.get_vround_mode(); -int64_t int_max = (1 << (p->VU.vsew - 1)) - 1; -int64_t int_min = -(1 << (p->VU.vsew - 1)); +VRM xrm = P.VU.get_vround_mode(); +int64_t int_max = (1 << (P.VU.vsew - 1)) - 1; +int64_t int_min = -(1 << (P.VU.vsew - 1)); VI_VVXI_LOOP_NARROW ({ diff --git a/riscv/insns/vnclip_vv.h b/riscv/insns/vnclip_vv.h index cce5ace..f1a823e 100644 --- a/riscv/insns/vnclip_vv.h +++ b/riscv/insns/vnclip_vv.h @@ -1,7 +1,7 @@ // vnclip: vd[i] = clip(round(vs2[i] + rnd) >> vs1[i]) -VRM xrm = p->VU.get_vround_mode(); -int64_t int_max = (1 << (p->VU.vsew - 1)) - 1; -int64_t int_min = -(1 << (p->VU.vsew - 1)); +VRM xrm = P.VU.get_vround_mode(); +int64_t int_max = (1 << (P.VU.vsew - 1)) - 1; +int64_t int_min = -(1 << (P.VU.vsew - 1)); VI_VVXI_LOOP_NARROW ({ diff --git a/riscv/insns/vnclip_vx.h b/riscv/insns/vnclip_vx.h index ca96a47..cb86f76 100644 --- a/riscv/insns/vnclip_vx.h +++ b/riscv/insns/vnclip_vx.h @@ -1,7 +1,7 @@ // vnclip: vd[i] = clip(round(vs2[i] + rnd) >> rs1[i]) -VRM xrm = p->VU.get_vround_mode(); -int64_t int_max = (1 << (p->VU.vsew - 1)) - 1; -int64_t int_min = -(1 << (p->VU.vsew - 1)); +VRM xrm = P.VU.get_vround_mode(); +int64_t int_max = (1 << (P.VU.vsew - 1)) - 1; +int64_t int_min = -(1 << (P.VU.vsew - 1)); VI_VVXI_LOOP_NARROW ({ diff --git a/riscv/insns/vnclipu_vi.h b/riscv/insns/vnclipu_vi.h index f57fd14..0c57eb7 100644 --- a/riscv/insns/vnclipu_vi.h +++ b/riscv/insns/vnclipu_vi.h @@ -1,6 +1,6 @@ // vnclipu: vd[i] = clip(round(vs2[i] + rnd) >> simm) -VRM xrm = p->VU.get_vround_mode(); -uint64_t int_max = ~(-1ll << p->VU.vsew); +VRM xrm = P.VU.get_vround_mode(); +uint64_t int_max = ~(-1ll << P.VU.vsew); VI_VVXI_LOOP_NARROW ({ uint64_t result = vs2_u; @@ -13,7 +13,7 @@ VI_VVXI_LOOP_NARROW // saturation if (result & (uint64_t)(-1ll << sew)){ result = int_max; - p->VU.vxsat = 1; + P.VU.vxsat = 1; } vd = result; diff --git a/riscv/insns/vnclipu_vv.h b/riscv/insns/vnclipu_vv.h index 8a60ade..8b19a0e 100644 --- a/riscv/insns/vnclipu_vv.h +++ b/riscv/insns/vnclipu_vv.h @@ -1,6 +1,6 @@ // vnclipu: vd[i] = clip(round(vs2[i] + rnd) >> vs1[i]) -VRM xrm = p->VU.get_vround_mode(); -uint64_t int_max = ~(-1ll << p->VU.vsew); +VRM xrm = P.VU.get_vround_mode(); +uint64_t int_max = ~(-1ll << P.VU.vsew); VI_VVXI_LOOP_NARROW ({ @@ -19,7 +19,7 @@ VI_VVXI_LOOP_NARROW // saturation if (result & (uint64_t)(-1ll << sew)){ result = int_max; - p->VU.vxsat = 1; + P.VU.vxsat = 1; } vd = result; diff --git a/riscv/insns/vnclipu_vx.h b/riscv/insns/vnclipu_vx.h index a52cfdb..072a208 100644 --- a/riscv/insns/vnclipu_vx.h +++ b/riscv/insns/vnclipu_vx.h @@ -1,6 +1,6 @@ // vnclipu: vd[i] = clip(round(vs2[i] + rnd) >> rs1[i]) -VRM xrm = p->VU.get_vround_mode(); -uint64_t int_max = ~(-1ll << p->VU.vsew); +VRM xrm = P.VU.get_vround_mode(); +uint64_t int_max = ~(-1ll << P.VU.vsew); VI_VVXI_LOOP_NARROW ({ uint64_t result = vs2; @@ -19,7 +19,7 @@ VI_VVXI_LOOP_NARROW // saturation if (result & (uint64_t)(-1ll << sew)){ result = int_max; - p->VU.vxsat = 1; + P.VU.vxsat = 1; } vd = result; diff --git a/riscv/insns/vrgather_vi.h b/riscv/insns/vrgather_vi.h index 47a5a19..46b9867 100644 --- a/riscv/insns/vrgather_vi.h +++ b/riscv/insns/vrgather_vi.h @@ -1,8 +1,8 @@ // vrgather.vi vd, vs2, zimm5 vm # vd[i] = (zimm5 >= VLMAX) ? 0 : vs2[zimm5]; -require(p->VU.vsew >= e8 && p->VU.vsew <= e64); -require(!p->VU.vill); -reg_t vl = p->VU.vl; -reg_t sew = p->VU.vsew; +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); +require(!P.VU.vill); +reg_t vl = P.VU.vl; +reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); reg_t rs2_num = insn.rs2(); reg_t zimm5 = insn.v_zimm5(); diff --git a/riscv/insns/vrgather_vv.h b/riscv/insns/vrgather_vv.h index bdf5d8e..b93246c 100644 --- a/riscv/insns/vrgather_vv.h +++ b/riscv/insns/vrgather_vv.h @@ -1,8 +1,8 @@ // vrgather.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; -require(p->VU.vsew >= e8 && p->VU.vsew <= e64); -require(!p->VU.vill); -reg_t vl = p->VU.vl; -reg_t sew = p->VU.vsew; +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); +require(!P.VU.vill); +reg_t vl = P.VU.vl; +reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); reg_t rs1_num = insn.rs1(); reg_t rs2_num = insn.rs2(); diff --git a/riscv/insns/vrgather_vx.h b/riscv/insns/vrgather_vx.h index 29ee011..629a2ee 100644 --- a/riscv/insns/vrgather_vx.h +++ b/riscv/insns/vrgather_vx.h @@ -1,8 +1,8 @@ // vrgather.vx vd, vs2, rs1, vm # vd[i] = (rs1 >= VLMAX) ? 0 : vs2[rs1]; -require(p->VU.vsew >= e8 && p->VU.vsew <= e64); -require(!p->VU.vill); -reg_t vl = p->VU.vl; -reg_t sew = p->VU.vsew; +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); +require(!P.VU.vill); +reg_t vl = P.VU.vl; +reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); reg_t rs1_num = insn.rs1(); reg_t rs2_num = insn.rs2(); diff --git a/riscv/insns/vsaddu_vi.h b/riscv/insns/vsaddu_vi.h index bd00c25..678cd0b 100644 --- a/riscv/insns/vsaddu_vi.h +++ b/riscv/insns/vsaddu_vi.h @@ -7,6 +7,6 @@ VI_VI_ULOOP sat = vd < vs2; vd |= -(vd < vs2); - p->VU.vxsat |= sat; + P.VU.vxsat |= sat; }) VI_CHECK_1905 diff --git a/riscv/insns/vsaddu_vv.h b/riscv/insns/vsaddu_vv.h index cdf810a..d29ee06 100644 --- a/riscv/insns/vsaddu_vv.h +++ b/riscv/insns/vsaddu_vv.h @@ -7,6 +7,6 @@ VI_VV_ULOOP sat = vd < vs2; vd |= -(vd < vs2); - p->VU.vxsat |= sat; + P.VU.vxsat |= sat; }) VI_CHECK_1905 diff --git a/riscv/insns/vsaddu_vx.h b/riscv/insns/vsaddu_vx.h index eba35bc..7747409 100644 --- a/riscv/insns/vsaddu_vx.h +++ b/riscv/insns/vsaddu_vx.h @@ -7,7 +7,7 @@ VI_VX_ULOOP sat = vd < vs2; vd |= -(vd < vs2); - p->VU.vxsat |= sat; + P.VU.vxsat |= sat; }) VI_CHECK_1905 diff --git a/riscv/insns/vsb_v.h b/riscv/insns/vsb_v.h index 47838e4..ca4ca8f 100644 --- a/riscv/insns/vsb_v.h +++ b/riscv/insns/vsb_v.h @@ -1,11 +1,11 @@ // vsb.v and vsseg[2-8]b.v -require(p->VU.vsew >= e8); +require(P.VU.vsew >= e8); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t vs3 = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; STRIP(i) @@ -16,23 +16,23 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { uint8_t val = 0; - switch (p->VU.vsew) { + switch (P.VU.vsew) { case e8: - val = p->VU.elt<uint8_t>(vs3 + fn, vreg_inx); + val = P.VU.elt<uint8_t>(vs3 + fn, vreg_inx); break; case e16: - val = p->VU.elt<uint16_t>(vs3 + fn, vreg_inx); + val = P.VU.elt<uint16_t>(vs3 + fn, vreg_inx); break; case e32: - val = p->VU.elt<uint32_t>(vs3 + fn, vreg_inx); + val = P.VU.elt<uint32_t>(vs3 + fn, vreg_inx); break; default: - val = p->VU.elt<uint64_t>(vs3 + fn, vreg_inx); + val = P.VU.elt<uint64_t>(vs3 + fn, vreg_inx); break; } MMU.store_uint8(baseAddr + (i * nf + fn) * 1, val); } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vsbc_vv.h b/riscv/insns/vsbc_vv.h index 7a872ca..d5fe37d 100644 --- a/riscv/insns/vsbc_vv.h +++ b/riscv/insns/vsbc_vv.h @@ -1,6 +1,6 @@ // vsbc.vv vd, vs2, rs1 require(insn.v_vm() == 1); -require(!(insn.rd() == 0 && p->VU.vlmul > 1)); +require(!(insn.rd() == 0 && P.VU.vlmul > 1)); VI_VV_LOOP ({ auto &v0 = P.VU.elt<uint64_t>(0, midx); diff --git a/riscv/insns/vsbc_vx.h b/riscv/insns/vsbc_vx.h index 4ad5c8a..4d6c911 100644 --- a/riscv/insns/vsbc_vx.h +++ b/riscv/insns/vsbc_vx.h @@ -1,6 +1,6 @@ // vsbc.vx vd, vs2, rs1 require(insn.v_vm() == 1); -require(!(insn.rd() == 0 && p->VU.vlmul > 1)); +require(!(insn.rd() == 0 && P.VU.vlmul > 1)); VI_VX_ULOOP ({ auto &v0 = P.VU.elt<uint64_t>(0, midx); diff --git a/riscv/insns/vse_v.h b/riscv/insns/vse_v.h index bb4c0b9..ea4841e 100644 --- a/riscv/insns/vse_v.h +++ b/riscv/insns/vse_v.h @@ -1,13 +1,13 @@ // vsw.v and vsseg[2-8]w.v -const reg_t sew = p->VU.vsew; +const reg_t sew = P.VU.vsew; const reg_t nf = insn.v_nf() + 1; -const reg_t vl = p->VU.vl; +const reg_t vl = P.VU.vl; const reg_t elt_byte = sew / 8; require(sew >= e8 && sew <= e64); -require((nf * p->VU.vlmul) <= (NVPR / 4)); +require((nf * P.VU.vlmul) <= (NVPR / 4)); reg_t baseAddr = RS1; reg_t vs3 = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; V_ELEMENT_SKIP(i); @@ -37,5 +37,5 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vsetvl.h b/riscv/insns/vsetvl.h index 429e5c0..773b984 100644 --- a/riscv/insns/vsetvl.h +++ b/riscv/insns/vsetvl.h @@ -1 +1 @@ -WRITE_RD(p->VU.set_vl(insn.rs1(), RS1, RS2)); +WRITE_RD(P.VU.set_vl(insn.rs1(), RS1, RS2)); diff --git a/riscv/insns/vsetvli.h b/riscv/insns/vsetvli.h index 0f4d4a6..fc5d1ba 100644 --- a/riscv/insns/vsetvli.h +++ b/riscv/insns/vsetvli.h @@ -1 +1 @@ -WRITE_RD(p->VU.set_vl(insn.rs1(), RS1, insn.v_zimm11())); +WRITE_RD(P.VU.set_vl(insn.rs1(), RS1, insn.v_zimm11())); diff --git a/riscv/insns/vsh_v.h b/riscv/insns/vsh_v.h index 075a9ff..dfaf2b9 100644 --- a/riscv/insns/vsh_v.h +++ b/riscv/insns/vsh_v.h @@ -1,11 +1,11 @@ // vsh.v and vsseg[2-8]h.v -require(p->VU.vsew >= e16); +require(P.VU.vsew >= e16); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t vs3 = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; V_ELEMENT_SKIP(i); @@ -16,20 +16,20 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { uint16_t val = 0; - switch (p->VU.vsew) { + switch (P.VU.vsew) { case e16: - val = p->VU.elt<uint16_t>(vs3 + fn, vreg_inx); + val = P.VU.elt<uint16_t>(vs3 + fn, vreg_inx); break; case e32: - val = p->VU.elt<uint32_t>(vs3 + fn, vreg_inx); + val = P.VU.elt<uint32_t>(vs3 + fn, vreg_inx); break; default: - val = p->VU.elt<uint64_t>(vs3 + fn, vreg_inx); + val = P.VU.elt<uint64_t>(vs3 + fn, vreg_inx); break; } MMU.store_uint16(baseAddr + (i * nf + fn) * 2, val); } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vsmul_vv.h b/riscv/insns/vsmul_vv.h index 1e4c3ee..f4876d7 100644 --- a/riscv/insns/vsmul_vv.h +++ b/riscv/insns/vsmul_vv.h @@ -1,8 +1,8 @@ // vsmul: Signed saturating and rounding fractional multiply -VRM xrm = p->VU.get_vround_mode(); -uint64_t int_max = (1ul << (p->VU.vsew - 1)) - 1; -uint64_t int_min = - (1 << (p->VU.vsew - 1)); -uint64_t sign_mask = ((1ul << (p->VU.vsew - 1))); +VRM xrm = P.VU.get_vround_mode(); +uint64_t int_max = (1ul << (P.VU.vsew - 1)) - 1; +uint64_t int_min = - (1 << (P.VU.vsew - 1)); +uint64_t sign_mask = ((1ul << (P.VU.vsew - 1))); VI_VV_ULOOP ({ @@ -25,7 +25,7 @@ VI_VV_ULOOP // saturation if (overflow){ result = int_max; - p->VU.vxsat = 1; + P.VU.vxsat = 1; }else{ result |= result_sign; } diff --git a/riscv/insns/vsmul_vx.h b/riscv/insns/vsmul_vx.h index fa522a1..5596c65 100644 --- a/riscv/insns/vsmul_vx.h +++ b/riscv/insns/vsmul_vx.h @@ -1,8 +1,8 @@ // vsmul -VRM xrm = p->VU.get_vround_mode(); -uint128_t int_max = (1ul << (p->VU.vsew - 1)) - 1; -uint128_t int_min = - (1 << (p->VU.vsew - 1)); -uint128_t sign_mask = ((1ul << (p->VU.vsew - 1))); +VRM xrm = P.VU.get_vround_mode(); +uint128_t int_max = (1ul << (P.VU.vsew - 1)) - 1; +uint128_t int_min = - (1 << (P.VU.vsew - 1)); +uint128_t sign_mask = ((1ul << (P.VU.vsew - 1))); VI_VX_ULOOP ({ @@ -26,7 +26,7 @@ VI_VX_ULOOP // saturation if (overflow) { result = int_max; - p->VU.vxsat = 1; + P.VU.vxsat = 1; }else { result |= result_sign; } diff --git a/riscv/insns/vssb_v.h b/riscv/insns/vssb_v.h index ca3dcfb..25ff5c4 100644 --- a/riscv/insns/vssb_v.h +++ b/riscv/insns/vssb_v.h @@ -1,30 +1,30 @@ // vssb.v and vssseg[2-8]b.v -require(p->VU.vsew >= e8); +require(P.VU.vsew >= e8); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = RS2; reg_t vs3 = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; STRIP(i) V_ELEMENT_SKIP(i); for (reg_t fn = 0; fn < nf; ++fn) { uint8_t val = 0; - switch (p->VU.vsew) { + switch (P.VU.vsew) { case e8: - val = p->VU.elt<uint8_t>(vs3 + fn, vreg_inx); + val = P.VU.elt<uint8_t>(vs3 + fn, vreg_inx); break; case e16: - val = p->VU.elt<uint16_t>(vs3 + fn, vreg_inx); + val = P.VU.elt<uint16_t>(vs3 + fn, vreg_inx); break; case e32: - val = p->VU.elt<uint32_t>(vs3 + fn, vreg_inx); + val = P.VU.elt<uint32_t>(vs3 + fn, vreg_inx); break; default: - val = p->VU.elt<uint64_t>(vs3 + fn, vreg_inx); + val = P.VU.elt<uint64_t>(vs3 + fn, vreg_inx); break; } if (is_valid){ @@ -33,5 +33,5 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vsse_v.h b/riscv/insns/vsse_v.h index 6b25bde..0f5837b 100644 --- a/riscv/insns/vsse_v.h +++ b/riscv/insns/vsse_v.h @@ -1,14 +1,14 @@ // vsse.v and vssseg[2-8]e.v -const reg_t sew = p->VU.vsew; +const reg_t sew = P.VU.vsew; const reg_t nf = insn.v_nf() + 1; -const reg_t vl = p->VU.vl; +const reg_t vl = P.VU.vl; const reg_t elt_byte = sew / 8; require(sew >= e8 && sew <= e64); -require((nf * p->VU.vlmul) <= (NVPR / 4)); +require((nf * P.VU.vlmul) <= (NVPR / 4)); reg_t baseAddr = RS1; reg_t stride = RS2; reg_t vs3 = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; V_ELEMENT_SKIP(i); @@ -21,22 +21,22 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { switch (sew) { case e8: MMU.store_uint8(baseAddr + i * stride + fn * elt_byte, - p->VU.elt<uint8_t>(vs3 + fn, vreg_inx)); + P.VU.elt<uint8_t>(vs3 + fn, vreg_inx)); break; case e16: MMU.store_uint16(baseAddr + i * stride + fn * elt_byte, - p->VU.elt<uint16_t>(vs3 + fn, vreg_inx)); + P.VU.elt<uint16_t>(vs3 + fn, vreg_inx)); break; case e32: MMU.store_uint32(baseAddr + i * stride + fn * elt_byte, - p->VU.elt<uint32_t>(vs3 + fn, vreg_inx)); + P.VU.elt<uint32_t>(vs3 + fn, vreg_inx)); break; case e64: MMU.store_uint64(baseAddr + i * stride + fn * elt_byte, - p->VU.elt<uint64_t>(vs3 + fn, vreg_inx)); + P.VU.elt<uint64_t>(vs3 + fn, vreg_inx)); break; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vssh_v.h b/riscv/insns/vssh_v.h index 70c5fa5..1a062cf 100644 --- a/riscv/insns/vssh_v.h +++ b/riscv/insns/vssh_v.h @@ -1,12 +1,12 @@ // vssh.v and vssseg[2-8]h.v -require(p->VU.vsew >= e16); +require(P.VU.vsew >= e16); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = RS2; reg_t vs3 = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; STRIP(i) @@ -14,20 +14,20 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { uint16_t val = 0; - switch (p->VU.vsew) { + switch (P.VU.vsew) { case e16: - val = p->VU.elt<uint16_t>(vs3 + fn, vreg_inx); + val = P.VU.elt<uint16_t>(vs3 + fn, vreg_inx); break; case e32: - val = p->VU.elt<uint32_t>(vs3 + fn, vreg_inx); + val = P.VU.elt<uint32_t>(vs3 + fn, vreg_inx); break; default: - val = p->VU.elt<uint64_t>(vs3 + fn, vreg_inx); + val = P.VU.elt<uint64_t>(vs3 + fn, vreg_inx); break; } if (is_valid) MMU.store_uint16(baseAddr + i * stride + fn * 2, val); } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vssra_vi.h b/riscv/insns/vssra_vi.h index 6bf66da..acd9413 100644 --- a/riscv/insns/vssra_vi.h +++ b/riscv/insns/vssra_vi.h @@ -1,5 +1,5 @@ // vssra.vi vd, vs2, simm5 -VRM xrm = p->VU.get_vround_mode(); +VRM xrm = P.VU.get_vround_mode(); VI_VI_LOOP ({ int64_t v2 = vs2; diff --git a/riscv/insns/vssra_vv.h b/riscv/insns/vssra_vv.h index c65ad9d..642ec9e 100644 --- a/riscv/insns/vssra_vv.h +++ b/riscv/insns/vssra_vv.h @@ -1,5 +1,5 @@ // vssra.vv vd, vs2, vs1 -VRM xrm = p->VU.get_vround_mode(); +VRM xrm = P.VU.get_vround_mode(); VI_VV_LOOP ({ int64_t v2 = vs2; diff --git a/riscv/insns/vssra_vx.h b/riscv/insns/vssra_vx.h index b9c8579..7e40f4e 100644 --- a/riscv/insns/vssra_vx.h +++ b/riscv/insns/vssra_vx.h @@ -1,5 +1,5 @@ // vssra.vx vd, vs2, rs1 -VRM xrm = p->VU.get_vround_mode(); +VRM xrm = P.VU.get_vround_mode(); VI_VX_LOOP ({ int64_t v2 = vs2; diff --git a/riscv/insns/vssrl_vi.h b/riscv/insns/vssrl_vi.h index 234b370..328d29c 100644 --- a/riscv/insns/vssrl_vi.h +++ b/riscv/insns/vssrl_vi.h @@ -1,5 +1,5 @@ // vssra.vi vd, vs2, simm5 -VRM xrm = p->VU.get_vround_mode(); +VRM xrm = P.VU.get_vround_mode(); VI_VI_ULOOP ({ uint64_t v2 = vs2; diff --git a/riscv/insns/vssrl_vv.h b/riscv/insns/vssrl_vv.h index ec167b9..1b79d04 100644 --- a/riscv/insns/vssrl_vv.h +++ b/riscv/insns/vssrl_vv.h @@ -1,5 +1,5 @@ // vssrl.vv vd, vs2, vs1 -VRM xrm = p->VU.get_vround_mode(); +VRM xrm = P.VU.get_vround_mode(); VI_VV_ULOOP ({ uint64_t v2 = vs2; diff --git a/riscv/insns/vssrl_vx.h b/riscv/insns/vssrl_vx.h index 1a7de9d..9d7746e 100644 --- a/riscv/insns/vssrl_vx.h +++ b/riscv/insns/vssrl_vx.h @@ -1,5 +1,5 @@ // vssrl.vx vd, vs2, rs1 -VRM xrm = p->VU.get_vround_mode(); +VRM xrm = P.VU.get_vround_mode(); VI_VX_ULOOP ({ uint64_t v2 = vs2; diff --git a/riscv/insns/vssub_vv.h b/riscv/insns/vssub_vv.h index a1541bc..c9683bf 100644 --- a/riscv/insns/vssub_vv.h +++ b/riscv/insns/vssub_vv.h @@ -24,6 +24,6 @@ VI_LOOP_BASE break; } } - p->VU.vxsat |= sat; + P.VU.vxsat |= sat; VI_LOOP_END VI_CHECK_1905 diff --git a/riscv/insns/vssub_vx.h b/riscv/insns/vssub_vx.h index fa5ccbe..dc3e4f6 100644 --- a/riscv/insns/vssub_vx.h +++ b/riscv/insns/vssub_vx.h @@ -24,6 +24,6 @@ VI_LOOP_BASE break; } } - p->VU.vxsat |= sat; + P.VU.vxsat |= sat; VI_LOOP_END VI_CHECK_1905 diff --git a/riscv/insns/vssubu_vv.h b/riscv/insns/vssubu_vv.h index 9767317..57ff450 100644 --- a/riscv/insns/vssubu_vv.h +++ b/riscv/insns/vssubu_vv.h @@ -24,7 +24,7 @@ VI_LOOP_BASE break; } } - p->VU.vxsat |= sat; + P.VU.vxsat |= sat; VI_LOOP_END VI_CHECK_1905 diff --git a/riscv/insns/vssubu_vx.h b/riscv/insns/vssubu_vx.h index e89997a..b5f5854 100644 --- a/riscv/insns/vssubu_vx.h +++ b/riscv/insns/vssubu_vx.h @@ -24,6 +24,6 @@ VI_LOOP_BASE break; } } - p->VU.vxsat |= sat; + P.VU.vxsat |= sat; VI_LOOP_END VI_CHECK_1905 diff --git a/riscv/insns/vssw_v.h b/riscv/insns/vssw_v.h index 834c05b..c83607b 100644 --- a/riscv/insns/vssw_v.h +++ b/riscv/insns/vssw_v.h @@ -1,12 +1,12 @@ // vssw.v and vssseg[2-8]w.v -require(p->VU.vsew >= e32); +require(P.VU.vsew >= e32); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = RS2; reg_t vs3 = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; STRIP(i) @@ -14,17 +14,17 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { uint32_t val = 0; - switch (p->VU.vsew) { + switch (P.VU.vsew) { case e32: - val = p->VU.elt<uint32_t>(vs3 + fn, vreg_inx); + val = P.VU.elt<uint32_t>(vs3 + fn, vreg_inx); break; default: - val = p->VU.elt<uint64_t>(vs3 + fn, vreg_inx); + val = P.VU.elt<uint64_t>(vs3 + fn, vreg_inx); break; } if (is_valid) MMU.store_uint32(baseAddr + i * stride + fn * 4, val); } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vsuxb_v.h b/riscv/insns/vsuxb_v.h index bddb228..7c1bba2 100644 --- a/riscv/insns/vsuxb_v.h +++ b/riscv/insns/vsuxb_v.h @@ -1,38 +1,38 @@ // vsuxb.v and vsxseg[2-8]b.v -require(p->VU.vsew >= e8); -reg_t vl = p->VU.vl; +require(P.VU.vsew >= e8); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vs3 = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; DUPLICATE_VREG(stride, vlmax); for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; V_ELEMENT_SKIP(i); STRIP(i) - switch (p->VU.vsew) { + switch (P.VU.vsew) { case e8: if (is_valid) MMU.store_uint8(baseAddr + index[i], - p->VU.elt<uint8_t>(vs3, vreg_inx)); + P.VU.elt<uint8_t>(vs3, vreg_inx)); break; case e16: if (is_valid) MMU.store_uint8(baseAddr + index[i], - p->VU.elt<uint16_t>(vs3, vreg_inx)); + P.VU.elt<uint16_t>(vs3, vreg_inx)); break; case e32: if (is_valid) MMU.store_uint8(baseAddr + index[i], - p->VU.elt<uint32_t>(vs3, vreg_inx)); + P.VU.elt<uint32_t>(vs3, vreg_inx)); break; case e64: if (is_valid) MMU.store_uint8(baseAddr + index[i], - p->VU.elt<uint64_t>(vs3, vreg_inx)); + P.VU.elt<uint64_t>(vs3, vreg_inx)); break; } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vsuxe_v.h b/riscv/insns/vsuxe_v.h index 2bf6917..a53bc0e 100644 --- a/riscv/insns/vsuxe_v.h +++ b/riscv/insns/vsuxe_v.h @@ -1,11 +1,11 @@ // vsxe.v and vsxseg[2-8]e.v -const reg_t sew = p->VU.vsew; -const reg_t vl = p->VU.vl; +const reg_t sew = P.VU.vsew; +const reg_t vl = P.VU.vl; require(sew >= e8 && sew <= e64); reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vs3 = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; DUPLICATE_VREG(stride, vlmax); for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; @@ -16,24 +16,24 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { case e8: if (is_valid) MMU.store_uint8(baseAddr + index[i], - p->VU.elt<uint8_t>(vs3, vreg_inx)); + P.VU.elt<uint8_t>(vs3, vreg_inx)); break; case e16: if (is_valid) MMU.store_uint16(baseAddr + index[i], - p->VU.elt<uint16_t>(vs3, vreg_inx)); + P.VU.elt<uint16_t>(vs3, vreg_inx)); break; case e32: if (is_valid) MMU.store_uint32(baseAddr + index[i], - p->VU.elt<uint32_t>(vs3, vreg_inx)); + P.VU.elt<uint32_t>(vs3, vreg_inx)); break; case e64: if (is_valid) MMU.store_uint64(baseAddr + index[i], - p->VU.elt<uint64_t>(vs3, vreg_inx)); + P.VU.elt<uint64_t>(vs3, vreg_inx)); break; } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vsuxh_v.h b/riscv/insns/vsuxh_v.h index b79e603..e91555f 100644 --- a/riscv/insns/vsuxh_v.h +++ b/riscv/insns/vsuxh_v.h @@ -1,33 +1,33 @@ // vsxh.v and vsxseg[2-8]h.v -require(p->VU.vsew >= e16); -reg_t vl = p->VU.vl; +require(P.VU.vsew >= e16); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vs3 = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; DUPLICATE_VREG(stride, vlmax); for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; V_ELEMENT_SKIP(i); STRIP(i) - switch (p->VU.vsew) { + switch (P.VU.vsew) { case e16: if (is_valid) MMU.store_uint16(baseAddr + index[i], - p->VU.elt<uint16_t>(vs3, vreg_inx)); + P.VU.elt<uint16_t>(vs3, vreg_inx)); break; case e32: if (is_valid) MMU.store_uint16(baseAddr + index[i], - p->VU.elt<uint32_t>(vs3, vreg_inx)); + P.VU.elt<uint32_t>(vs3, vreg_inx)); break; case e64: if (is_valid) MMU.store_uint16(baseAddr + index[i], - p->VU.elt<uint64_t>(vs3, vreg_inx)); + P.VU.elt<uint64_t>(vs3, vreg_inx)); break; } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vsuxw_v.h b/riscv/insns/vsuxw_v.h index 49b41d0..edf46cd 100644 --- a/riscv/insns/vsuxw_v.h +++ b/riscv/insns/vsuxw_v.h @@ -1,28 +1,28 @@ // vsxw.v and vsxseg[2-8]w.v -require(p->VU.vsew >= e32); -reg_t vl = p->VU.vl; +require(P.VU.vsew >= e32); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vs3 = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; DUPLICATE_VREG(stride, vlmax); for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; V_ELEMENT_SKIP(i); STRIP(i) - switch (p->VU.vsew) { + switch (P.VU.vsew) { case e32: if (is_valid) MMU.store_uint32(baseAddr + index[i], - p->VU.elt<uint32_t>(vs3, vreg_inx)); + P.VU.elt<uint32_t>(vs3, vreg_inx)); break; case e64: if (is_valid) MMU.store_uint32(baseAddr + index[i], - p->VU.elt<uint64_t>(vs3, vreg_inx)); + P.VU.elt<uint64_t>(vs3, vreg_inx)); break; } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vsw_v.h b/riscv/insns/vsw_v.h index 049e34e..0f5804c 100644 --- a/riscv/insns/vsw_v.h +++ b/riscv/insns/vsw_v.h @@ -1,11 +1,11 @@ // vsw.v and vsseg[2-8]w.v -require(p->VU.vsew >= e32); +require(P.VU.vsew >= e32); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t vs3 = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; STRIP(i) @@ -16,19 +16,19 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { for (reg_t fn = 0; fn < nf; ++fn){ uint32_t val = 0; - switch (p->VU.vsew) { + switch (P.VU.vsew) { case e32: - val = p->VU.elt<uint32_t>(vs3 + fn, vreg_inx); + val = P.VU.elt<uint32_t>(vs3 + fn, vreg_inx); break; default: - val = p->VU.elt<uint64_t>(vs3 + fn, vreg_inx); + val = P.VU.elt<uint64_t>(vs3 + fn, vreg_inx); break; } MMU.store_uint32(baseAddr + (i * nf + fn) * 4, val); } } -p->VU.vstart = 0; +P.VU.vstart = 0; if (nf >= 2) { VI_CHECK_1905; } diff --git a/riscv/insns/vsxb_v.h b/riscv/insns/vsxb_v.h index 740285d..e9054dc 100644 --- a/riscv/insns/vsxb_v.h +++ b/riscv/insns/vsxb_v.h @@ -1,12 +1,12 @@ // vsxb.v and vsxseg[2-8]b.v -require(p->VU.vsew >= e8); +require(P.VU.vsew >= e8); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vs3 = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; DUPLICATE_VREG(stride, vlmax); for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; @@ -14,29 +14,29 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { STRIP(i) for (reg_t fn = 0; fn < nf; ++fn) { - switch (p->VU.vsew) { + switch (P.VU.vsew) { case e8: if (is_valid) MMU.store_uint8(baseAddr + index[i] + fn * 1, - p->VU.elt<uint8_t>(vs3 + fn, vreg_inx)); + P.VU.elt<uint8_t>(vs3 + fn, vreg_inx)); break; case e16: if (is_valid) MMU.store_uint8(baseAddr + index[i] + fn * 1, - p->VU.elt<uint16_t>(vs3 + fn, vreg_inx)); + P.VU.elt<uint16_t>(vs3 + fn, vreg_inx)); break; case e32: if (is_valid) MMU.store_uint8(baseAddr + index[i] + fn * 1, - p->VU.elt<uint32_t>(vs3 + fn, vreg_inx)); + P.VU.elt<uint32_t>(vs3 + fn, vreg_inx)); break; case e64: if (is_valid) MMU.store_uint8(baseAddr + index[i] + fn * 1, - p->VU.elt<uint64_t>(vs3 + fn, vreg_inx)); + P.VU.elt<uint64_t>(vs3 + fn, vreg_inx)); break; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vsxe_v.h b/riscv/insns/vsxe_v.h index e08db06..d9bec1b 100644 --- a/riscv/insns/vsxe_v.h +++ b/riscv/insns/vsxe_v.h @@ -1,14 +1,14 @@ // vsxe.v and vsxseg[2-8]e.v -const reg_t sew = p->VU.vsew; +const reg_t sew = P.VU.vsew; const reg_t nf = insn.v_nf() + 1; -const reg_t vl = p->VU.vl; +const reg_t vl = P.VU.vl; const reg_t elt_byte = sew / 8; require(sew >= e8 && sew <= e64); -require((nf * p->VU.vlmul) <= (NVPR / 4)); +require((nf * P.VU.vlmul) <= (NVPR / 4)); reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vs3 = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; DUPLICATE_VREG(stride, vlmax); for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; @@ -20,25 +20,25 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { case e8: if (is_valid) MMU.store_uint8(baseAddr + index[i] + fn * elt_byte, - p->VU.elt<uint8_t>(vs3 + fn, vreg_inx)); + P.VU.elt<uint8_t>(vs3 + fn, vreg_inx)); break; case e16: if (is_valid) MMU.store_uint16(baseAddr + index[i] + fn * elt_byte, - p->VU.elt<uint16_t>(vs3 + fn, vreg_inx)); + P.VU.elt<uint16_t>(vs3 + fn, vreg_inx)); break; case e32: if (is_valid) MMU.store_uint32(baseAddr + index[i] + fn * elt_byte, - p->VU.elt<uint32_t>(vs3 + fn, vreg_inx)); + P.VU.elt<uint32_t>(vs3 + fn, vreg_inx)); break; case e64: if (is_valid) MMU.store_uint64(baseAddr + index[i] + fn * elt_byte, - p->VU.elt<uint64_t>(vs3 + fn, vreg_inx)); + P.VU.elt<uint64_t>(vs3 + fn, vreg_inx)); break; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vsxh_v.h b/riscv/insns/vsxh_v.h index 20b8662..928095b 100644 --- a/riscv/insns/vsxh_v.h +++ b/riscv/insns/vsxh_v.h @@ -1,12 +1,12 @@ // vsxh.v and vsxseg[2-8]h.v -require(p->VU.vsew >= e16); +require(P.VU.vsew >= e16); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vs3 = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; DUPLICATE_VREG(stride, vlmax); for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; @@ -14,24 +14,24 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { STRIP(i) for (reg_t fn = 0; fn < nf; ++fn) { - switch (p->VU.vsew) { + switch (P.VU.vsew) { case e16: if (is_valid) MMU.store_uint16(baseAddr + index[i] + fn * 2, - p->VU.elt<uint16_t>(vs3 + fn, vreg_inx)); + P.VU.elt<uint16_t>(vs3 + fn, vreg_inx)); break; case e32: if (is_valid) MMU.store_uint16(baseAddr + index[i] + fn * 2, - p->VU.elt<uint32_t>(vs3 + fn, vreg_inx)); + P.VU.elt<uint32_t>(vs3 + fn, vreg_inx)); break; case e64: if (is_valid) MMU.store_uint16(baseAddr + index[i] + fn * 2, - p->VU.elt<uint64_t>(vs3 + fn, vreg_inx)); + P.VU.elt<uint64_t>(vs3 + fn, vreg_inx)); break; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vsxw_v.h b/riscv/insns/vsxw_v.h index c7040fc..5ec78e2 100644 --- a/riscv/insns/vsxw_v.h +++ b/riscv/insns/vsxw_v.h @@ -1,12 +1,12 @@ // vsxw.v and vsxseg[2-8]w.v -require(p->VU.vsew >= e32); +require(P.VU.vsew >= e32); reg_t nf = insn.v_nf() + 1; -require((nf * p->VU.vlmul) <= (NVPR / 4)); -reg_t vl = p->VU.vl; +require((nf * P.VU.vlmul) <= (NVPR / 4)); +reg_t vl = P.VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vs3 = insn.rd(); -reg_t vlmax = p->VU.vlmax; +reg_t vlmax = P.VU.vlmax; DUPLICATE_VREG(stride, vlmax); for (reg_t i = 0; i < vlmax && vl != 0; ++i) { bool is_valid = true; @@ -14,19 +14,19 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { STRIP(i) for (reg_t fn = 0; fn < nf; ++fn) { - switch (p->VU.vsew) { + switch (P.VU.vsew) { case e32: if (is_valid) MMU.store_uint32(baseAddr + index[i] + fn * 4, - p->VU.elt<uint32_t>(vs3 + fn, vreg_inx)); + P.VU.elt<uint32_t>(vs3 + fn, vreg_inx)); break; case e64: if (is_valid) MMU.store_uint32(baseAddr + index[i] + fn * 4, - p->VU.elt<uint64_t>(vs3 + fn, vreg_inx)); + P.VU.elt<uint64_t>(vs3 + fn, vreg_inx)); break; } } } -p->VU.vstart = 0; +P.VU.vstart = 0; VI_CHECK_1905 diff --git a/riscv/insns/vwmulsu_vv.h b/riscv/insns/vwmulsu_vv.h index aab4043..f02b3f2 100644 --- a/riscv/insns/vwmulsu_vv.h +++ b/riscv/insns/vwmulsu_vv.h @@ -2,15 +2,15 @@ VI_WIDE_CHECK_DSS(true); VI_VV_LOOP_WIDEN ({ - switch(p->VU.vsew) { + switch(P.VU.vsew) { case e8: - p->VU.elt<uint16_t>(rd_num, i) = (int16_t)(int8_t)vs2 * (int16_t)(uint8_t)vs1; + P.VU.elt<uint16_t>(rd_num, i) = (int16_t)(int8_t)vs2 * (int16_t)(uint8_t)vs1; break; case e16: - p->VU.elt<uint32_t>(rd_num, i) = (int32_t)(int16_t)vs2 * (int32_t)(uint16_t)vs1; + P.VU.elt<uint32_t>(rd_num, i) = (int32_t)(int16_t)vs2 * (int32_t)(uint16_t)vs1; break; default: - p->VU.elt<uint64_t>(rd_num, i) = (int64_t)(int32_t)vs2 * (int64_t)(uint32_t)vs1; + P.VU.elt<uint64_t>(rd_num, i) = (int64_t)(int32_t)vs2 * (int64_t)(uint32_t)vs1; break; } }) diff --git a/riscv/insns/vwmulsu_vx.h b/riscv/insns/vwmulsu_vx.h index 1f65501..ae79b1f 100644 --- a/riscv/insns/vwmulsu_vx.h +++ b/riscv/insns/vwmulsu_vx.h @@ -2,15 +2,15 @@ VI_WIDE_CHECK_DSS(false); VI_VX_LOOP_WIDEN ({ - switch(p->VU.vsew) { + switch(P.VU.vsew) { case e8: - p->VU.elt<uint16_t>(rd_num, i) = (int16_t)(int8_t)vs2 * (int16_t)(uint8_t)rs1; + P.VU.elt<uint16_t>(rd_num, i) = (int16_t)(int8_t)vs2 * (int16_t)(uint8_t)rs1; break; case e16: - p->VU.elt<uint32_t>(rd_num, i) = (int32_t)(int16_t)vs2 * (int32_t)(uint16_t)rs1; + P.VU.elt<uint32_t>(rd_num, i) = (int32_t)(int16_t)vs2 * (int32_t)(uint16_t)rs1; break; default: - p->VU.elt<uint64_t>(rd_num, i) = (int64_t)(int32_t)vs2 * (int64_t)(uint32_t)rs1; + P.VU.elt<uint64_t>(rd_num, i) = (int64_t)(int32_t)vs2 * (int64_t)(uint32_t)rs1; break; } }) |