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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-09 01:47:51 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-10 00:30:07 -0700 |
| commit | 3d0c10dcf8c4285948aa443216af660279378817 (patch) | |
| tree | 7aab4eef72d8e0afd5e134c5dce5bbbe013fc980 | |
| parent | 5086e5cb075ccbbf1eb931761c412e02e61567ff (diff) | |
| download | spike-3d0c10dcf8c4285948aa443216af660279378817.zip spike-3d0c10dcf8c4285948aa443216af660279378817.tar.gz spike-3d0c10dcf8c4285948aa443216af660279378817.tar.bz2 | |
rvv: vslide[1]up now allows mask overlap when LMUL=1
See https://github.com/riscv/riscv-v-spec/pull/407
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/insns/vslide1up_vx.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vslideup_vi.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vslideup_vx.h | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/riscv/insns/vslide1up_vx.h b/riscv/insns/vslide1up_vx.h index 214512a..5154259 100644 --- a/riscv/insns/vslide1up_vx.h +++ b/riscv/insns/vslide1up_vx.h @@ -2,7 +2,7 @@ require((insn.rs2() & (P.VU.vlmul - 1)) == 0); require((insn.rd() & (P.VU.vlmul - 1)) == 0); require(insn.rd() != insn.rs2()); -if (insn.v_vm() == 0) +if (insn.v_vm() == 0 && P.VU.vlmul > 1) require(insn.rd() != 0); VI_LOOP_BASE diff --git a/riscv/insns/vslideup_vi.h b/riscv/insns/vslideup_vi.h index 89591e4..99d30bc 100644 --- a/riscv/insns/vslideup_vi.h +++ b/riscv/insns/vslideup_vi.h @@ -2,7 +2,7 @@ require((insn.rs2() & (P.VU.vlmul - 1)) == 0); require((insn.rd() & (P.VU.vlmul - 1)) == 0); require(insn.rd() != insn.rs2()); -if (insn.v_vm() == 0) +if (insn.v_vm() == 0 && P.VU.vlmul > 1) require(insn.rd() != 0); const reg_t offset = insn.v_zimm5(); diff --git a/riscv/insns/vslideup_vx.h b/riscv/insns/vslideup_vx.h index b513caa..2d68a39 100644 --- a/riscv/insns/vslideup_vx.h +++ b/riscv/insns/vslideup_vx.h @@ -2,7 +2,7 @@ require((insn.rs2() & (P.VU.vlmul - 1)) == 0); require((insn.rd() & (P.VU.vlmul - 1)) == 0); require(insn.rd() != insn.rs2()); -if (insn.v_vm() == 0) +if (insn.v_vm() == 0 && P.VU.vlmul > 1) require(insn.rd() != 0); const reg_t offset = RS1; |