diff options
| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-04-15 07:58:47 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-04-15 07:58:47 +0800 |
| commit | 6f0fb68d5879999c31a8c9bb274a4f7f31bd89f1 (patch) | |
| tree | 67984a60bc5f61a8f9a353a85d9d887b21ec136f | |
| parent | b82d97a011315c9f0332c6dcd691f54ca1327d9e (diff) | |
| download | spike-6f0fb68d5879999c31a8c9bb274a4f7f31bd89f1.zip spike-6f0fb68d5879999c31a8c9bb274a4f7f31bd89f1.tar.gz spike-6f0fb68d5879999c31a8c9bb274a4f7f31bd89f1.tar.bz2 | |
Fix comments error in vfncvt_*_w.h
| -rw-r--r-- | riscv/insns/vfncvt_f_f_w.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vfncvt_f_x_w.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vfncvt_f_xu_w.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vfncvt_rod_f_f_w.h | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/riscv/insns/vfncvt_f_f_w.h b/riscv/insns/vfncvt_f_f_w.h index 12bd5a6..97de40e 100644 --- a/riscv/insns/vfncvt_f_f_w.h +++ b/riscv/insns/vfncvt_f_f_w.h @@ -1,4 +1,4 @@ -// vfncvt.f.f.v vd, vs2, vm +// vfncvt.f.f.w vd, vs2, vm VI_VFP_NCVT_FP_TO_FP( { vd = f32_to_f16(vs2); }, // BODY32 { vd = f64_to_f32(vs2); }, // BODY64 diff --git a/riscv/insns/vfncvt_f_x_w.h b/riscv/insns/vfncvt_f_x_w.h index d5a7b91..46f2d92 100644 --- a/riscv/insns/vfncvt_f_x_w.h +++ b/riscv/insns/vfncvt_f_x_w.h @@ -1,4 +1,4 @@ -// vfncvt.f.x.v vd, vs2, vm +// vfncvt.f.x.w vd, vs2, vm VI_VFP_NCVT_INT_TO_FP( { vd = i32_to_f16(vs2); }, // BODY32 { vd = i64_to_f32(vs2); }, // BODY64 diff --git a/riscv/insns/vfncvt_f_xu_w.h b/riscv/insns/vfncvt_f_xu_w.h index 71aaf68..729fb52 100644 --- a/riscv/insns/vfncvt_f_xu_w.h +++ b/riscv/insns/vfncvt_f_xu_w.h @@ -1,4 +1,4 @@ -// vfncvt.f.xu.v vd, vs2, vm +// vfncvt.f.xu.w vd, vs2, vm VI_VFP_NCVT_INT_TO_FP( { vd = ui32_to_f16(vs2); }, // BODY32 { vd = ui64_to_f32(vs2); }, // BODY64 diff --git a/riscv/insns/vfncvt_rod_f_f_w.h b/riscv/insns/vfncvt_rod_f_f_w.h index b36b761..93002dc 100644 --- a/riscv/insns/vfncvt_rod_f_f_w.h +++ b/riscv/insns/vfncvt_rod_f_f_w.h @@ -1,4 +1,4 @@ -// vfncvt.rod.f.f.v vd, vs2, vm +// vfncvt.rod.f.f.w vd, vs2, vm VI_VFP_NCVT_FP_TO_FP( { // BODY32 softfloat_roundingMode = softfloat_round_odd; |