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| author | Ryan Buchner <ryan.buchner@arilinc.com> | 2023-04-17 20:22:59 -0700 |
|---|---|---|
| committer | rbuchner <ryan.buchner@arilinc.com> | 2023-05-11 23:00:59 -0700 |
| commit | 2745d3139cefd1fc2b97bb9382188c59f15eced9 (patch) | |
| tree | 8e23f7142fce3d0907543b22a49797ed7af5a5a1 | |
| parent | bd675766091549e4fc1607f6106b0dce7dc03d21 (diff) | |
| download | spike-2745d3139cefd1fc2b97bb9382188c59f15eced9.zip spike-2745d3139cefd1fc2b97bb9382188c59f15eced9.tar.gz spike-2745d3139cefd1fc2b97bb9382188c59f15eced9.tar.bz2 | |
Use access_info within load_slow_path rather than xlate_flags
Fixes case 2 from https://github.com/riscv-software-src/riscv-isa-sim/issues/872
| -rw-r--r-- | riscv/mmu.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index db6c31e..be986fe 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -230,11 +230,11 @@ void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, xlate_flags_t if ((addr & (len - 1)) == 0) { load_slow_path_intrapage(len, bytes, access_info); } else { - bool gva = ((proc) ? proc->state.v : false) || xlate_flags.forced_virt; + bool gva = access_info.effective_virt; if (!is_misaligned_enabled()) throw trap_load_address_misaligned(gva, addr, 0, 0); - if (xlate_flags.lr) + if (access_info.flags.lr) throw trap_load_access_fault(gva, addr, 0, 0); reg_t len_page0 = std::min(len, PGSIZE - addr % PGSIZE); |