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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-06-08 20:04:17 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-06-08 20:04:17 -0700 |
| commit | f82d42cdefb72f23a5a98b7d93413caec7bf5c8d (patch) | |
| tree | 6c7b7cfae491bf3bb44193d94348dab7d75887ea | |
| parent | 68d0fcad8795b3245322cbbac07412e0312ee76f (diff) | |
| download | spike-f82d42cdefb72f23a5a98b7d93413caec7bf5c8d.zip spike-f82d42cdefb72f23a5a98b7d93413caec7bf5c8d.tar.gz spike-f82d42cdefb72f23a5a98b7d93413caec7bf5c8d.tar.bz2 | |
Add degenerate HW breakpoint implementation
| -rw-r--r-- | riscv/encoding.h | 18 | ||||
| -rw-r--r-- | riscv/processor.cc | 4 |
2 files changed, 22 insertions, 0 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index 032626e..b784322 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -100,6 +100,16 @@ #define EXT_IO_BASE 0x40000000 #define DRAM_BASE 0x80000000 +// breakpoint control fields +#define BPCONTROL_X 0x00000001 +#define BPCONTROL_W 0x00000002 +#define BPCONTROL_R 0x00000004 +#define BPCONTROL_U 0x00000008 +#define BPCONTROL_S 0x00000010 +#define BPCONTROL_H 0x00000020 +#define BPCONTROL_M 0x00000040 +#define BPCONTROL_MATCHCOND 0x00000180 + // page table entry (PTE) fields #define PTE_V 0x001 // Valid #define PTE_TYPE 0x01E // Type @@ -697,6 +707,10 @@ #define CSR_MSCYCLE_DELTA 0x704 #define CSR_MSTIME_DELTA 0x705 #define CSR_MSINSTRET_DELTA 0x706 +#define CSR_TDRSELECT 0x7a0 +#define CSR_TDRDATA1 0x7a1 +#define CSR_TDRDATA2 0x7a2 +#define CSR_TDRDATA3 0x7a3 #define CSR_DCSR 0x7b0 #define CSR_DPC 0x7b1 #define CSR_DSCRATCH 0x7b2 @@ -1003,6 +1017,10 @@ DECLARE_CSR(muinstret_delta, CSR_MUINSTRET_DELTA) DECLARE_CSR(mscycle_delta, CSR_MSCYCLE_DELTA) DECLARE_CSR(mstime_delta, CSR_MSTIME_DELTA) DECLARE_CSR(msinstret_delta, CSR_MSINSTRET_DELTA) +DECLARE_CSR(tdrselect, CSR_TDRSELECT) +DECLARE_CSR(tdrdata1, CSR_TDRDATA1) +DECLARE_CSR(tdrdata2, CSR_TDRDATA2) +DECLARE_CSR(tdrdata3, CSR_TDRDATA3) DECLARE_CSR(dcsr, CSR_DCSR) DECLARE_CSR(dpc, CSR_DPC) DECLARE_CSR(dscratch, CSR_DSCRATCH) diff --git a/riscv/processor.cc b/riscv/processor.cc index b120ddb..ed9a83b 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -482,6 +482,10 @@ reg_t processor_t::get_csr(int which) case CSR_MTVEC: return state.mtvec; case CSR_MEDELEG: return state.medeleg; case CSR_MIDELEG: return state.mideleg; + case CSR_TDRSELECT: return 0; + case CSR_TDRDATA1: return 0; + case CSR_TDRDATA2: return 0; + case CSR_TDRDATA3: return 0; case CSR_DCSR: { uint32_t v = 0; |