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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-06-09 14:20:54 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-06-09 14:20:54 -0700 |
| commit | f5ecf65e5e2c6e60355933b8a2aca230e8443ff5 (patch) | |
| tree | 74859b54f9888333bdada6a87bf97d431e001566 | |
| parent | ab2858e065f9fa62eec0c2d053b98e45b41f6675 (diff) | |
| download | spike-f5ecf65e5e2c6e60355933b8a2aca230e8443ff5.zip spike-f5ecf65e5e2c6e60355933b8a2aca230e8443ff5.tar.gz spike-f5ecf65e5e2c6e60355933b8a2aca230e8443ff5.tar.bz2 | |
Trap on tdrdata registers when tdrselect[XLEN-1]=0
| -rw-r--r-- | riscv/processor.cc | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index ed9a83b..dac5d5b 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -483,9 +483,6 @@ reg_t processor_t::get_csr(int which) case CSR_MEDELEG: return state.medeleg; case CSR_MIDELEG: return state.mideleg; case CSR_TDRSELECT: return 0; - case CSR_TDRDATA1: return 0; - case CSR_TDRDATA2: return 0; - case CSR_TDRDATA3: return 0; case CSR_DCSR: { uint32_t v = 0; |