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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-07-22 14:05:06 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-07-22 14:05:20 -0700 |
| commit | 5daafcde73f448a702356e049911b5677a1811c2 (patch) | |
| tree | 938362fc9f34cc694434e317ab9a923190da5c8c | |
| parent | 8a0e5d2ed32360a1a14d4d4bd503dbaee6ba1a94 (diff) | |
| download | spike-5daafcde73f448a702356e049911b5677a1811c2.zip spike-5daafcde73f448a702356e049911b5677a1811c2.tar.gz spike-5daafcde73f448a702356e049911b5677a1811c2.tar.bz2 | |
Set U bit in misa register
| -rw-r--r-- | riscv/processor.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 8c89e3f..8c267f4 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -84,6 +84,7 @@ void processor_t::parse_isa_string(const char* str) isa_string = "rv" + std::to_string(max_xlen) + p; isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode + isa |= 1L << ('u' - 'a'); // advertise support for user mode while (*p) { isa |= 1L << (*p - 'a'); |