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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-06-17 20:58:01 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-06-17 20:58:01 -0700 |
| commit | 03d4f0215827abea18f83d8da1c097ce937c543b (patch) | |
| tree | 7c6e4afc9401e2a1104ba735f28684e3de90c756 | |
| parent | f5ecf65e5e2c6e60355933b8a2aca230e8443ff5 (diff) | |
| download | spike-03d4f0215827abea18f83d8da1c097ce937c543b.zip spike-03d4f0215827abea18f83d8da1c097ce937c543b.tar.gz spike-03d4f0215827abea18f83d8da1c097ce937c543b.tar.bz2 | |
Merge sasid into sptbr
| -rw-r--r-- | riscv/encoding.h | 25 | ||||
| -rw-r--r-- | riscv/processor.cc | 18 |
2 files changed, 31 insertions, 12 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index b784322..fa2d2dc 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -101,14 +101,21 @@ #define DRAM_BASE 0x80000000 // breakpoint control fields -#define BPCONTROL_X 0x00000001 -#define BPCONTROL_W 0x00000002 -#define BPCONTROL_R 0x00000004 -#define BPCONTROL_U 0x00000008 -#define BPCONTROL_S 0x00000010 -#define BPCONTROL_H 0x00000020 -#define BPCONTROL_M 0x00000040 -#define BPCONTROL_MATCHCOND 0x00000180 +#define BPCONTROL_X 0x00000001 +#define BPCONTROL_W 0x00000002 +#define BPCONTROL_R 0x00000004 +#define BPCONTROL_U 0x00000008 +#define BPCONTROL_S 0x00000010 +#define BPCONTROL_H 0x00000020 +#define BPCONTROL_M 0x00000040 +#define BPCONTROL_BPMATCH 0x00000780 +#ifdef __riscv64 +# define BPCONTROL_BPAMASKMAX 0x0F80000000000000 +# define BPCONTROL_TDRTYPE 0xF000000000000000 +#else +# define BPCONTROL_BPAMASKMAX 0x0F800000 +# define BPCONTROL_TDRTYPE 0xF0000000 +#endif // page table entry (PTE) fields #define PTE_V 0x001 // Valid @@ -685,7 +692,6 @@ #define CSR_SBADADDR 0x143 #define CSR_SIP 0x144 #define CSR_SPTBR 0x180 -#define CSR_SASID 0x181 #define CSR_SCYCLE 0xd00 #define CSR_STIME 0xd01 #define CSR_SINSTRET 0xd02 @@ -995,7 +1001,6 @@ DECLARE_CSR(scause, CSR_SCAUSE) DECLARE_CSR(sbadaddr, CSR_SBADADDR) DECLARE_CSR(sip, CSR_SIP) DECLARE_CSR(sptbr, CSR_SPTBR) -DECLARE_CSR(sasid, CSR_SASID) DECLARE_CSR(scycle, CSR_SCYCLE) DECLARE_CSR(stime, CSR_STIME) DECLARE_CSR(sinstret, CSR_SINSTRET) diff --git a/riscv/processor.cc b/riscv/processor.cc index dac5d5b..f030dfa 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -283,6 +283,16 @@ static bool validate_vm(int max_xlen, reg_t vm) return vm == VM_MBARE; } +static int paddr_bits(reg_t vm) +{ + switch (vm) { + case VM_SV32: return 34; + case VM_SV39: return 50; + case VM_SV48: return 50; + default: abort(); + } +} + void processor_t::set_csr(int which, reg_t val) { val = zext_xlen(val); @@ -367,9 +377,14 @@ void processor_t::set_csr(int which, reg_t val) case CSR_SIE: return set_csr(CSR_MIE, (state.mie & ~state.mideleg) | (val & state.mideleg)); + case CSR_SPTBR: { + // upper bits of sptbr are the ASID; we only support ASID = 0 + reg_t vm = get_field(state.mstatus, MSTATUS_VM); + state.sptbr = val & (((reg_t)1 << (paddr_bits(vm) - PGSHIFT)) - 1); + break; + } case CSR_SEPC: state.sepc = val; break; case CSR_STVEC: state.stvec = val >> 2 << 2; break; - case CSR_SPTBR: state.sptbr = val; break; case CSR_SSCRATCH: state.sscratch = val; break; case CSR_SCAUSE: state.scause = val; break; case CSR_SBADADDR: state.sbadaddr = val; break; @@ -465,7 +480,6 @@ reg_t processor_t::get_csr(int which) return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1)); return state.scause; case CSR_SPTBR: return state.sptbr; - case CSR_SASID: return 0; case CSR_SSCRATCH: return state.sscratch; case CSR_MSTATUS: return state.mstatus; case CSR_MIP: return state.mip; |