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author | Andrew Waterman <andrew@sifive.com> | 2022-03-15 20:58:14 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2022-03-15 22:46:28 -0700 |
commit | f17413e22d35422e4430f7f6e190817b66cbd5e2 (patch) | |
tree | 0e9f7ef8410b1fa819ebe54de2e57c00e2be06d9 | |
parent | cb4bea96ddb175fb6b338db7c3e8ef17cb228025 (diff) | |
download | spike-f17413e22d35422e4430f7f6e190817b66cbd5e2.zip spike-f17413e22d35422e4430f7f6e190817b66cbd5e2.tar.gz spike-f17413e22d35422e4430f7f6e190817b66cbd5e2.tar.bz2 |
Rewrite sstatus_csr_t::enabled() for higher performance
Eliminate calls to base_status_csr_t::enabled() so that the various
read() calls can be inlined. Doing so also removes a redundant check of
sstatus_write_mask.
Schedule the most common exit path first.
-rw-r--r-- | riscv/csrs.cc | 21 | ||||
-rw-r--r-- | riscv/csrs.h | 7 |
2 files changed, 15 insertions, 13 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 761a198..51fb3ef 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -316,12 +316,6 @@ base_status_csr_t::base_status_csr_t(processor_t* const proc, const reg_t addr): } -bool base_status_csr_t::enabled(const reg_t which) { - // If the field doesn't exist, it is always enabled. See #823. - if ((sstatus_write_mask & which) == 0) return true; - return (read() & which) != 0; -} - reg_t base_status_csr_t::compute_sstatus_write_mask() const noexcept { // If a configuration has FS bits, they will always be accessible no // matter the state of misa. @@ -471,11 +465,16 @@ void sstatus_csr_t::dirty(const reg_t dirties) { } bool sstatus_csr_t::enabled(const reg_t which) { - if (!orig_sstatus->enabled(which)) - return false; - if (state->v && !virt_sstatus->enabled(which)) - return false; - return true; + if ((orig_sstatus->read() & which) != 0) { + if (!state->v || (virt_sstatus->read() & which) != 0) + return true; + } + + // If the field doesn't exist, it is always enabled. See #823. + if (!orig_sstatus->field_exists(which)) + return true; + + return false; } diff --git a/riscv/csrs.h b/riscv/csrs.h index c0f5771..946d06c 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -185,8 +185,11 @@ class cause_csr_t: public basic_csr_t { class base_status_csr_t: public csr_t { public: base_status_csr_t(processor_t* const proc, const reg_t addr); - // Return true if the specified bits are not 00 (Off) - bool enabled(const reg_t which); + + bool field_exists(const reg_t which) { + return (sstatus_write_mask & which) != 0; + } + protected: reg_t adjust_sd(const reg_t val) const noexcept; void maybe_flush_tlb(const reg_t newval) noexcept; |