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author | Andrew Waterman <andrew@sifive.com> | 2022-05-13 13:58:53 -0700 |
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committer | GitHub <noreply@github.com> | 2022-05-13 13:58:53 -0700 |
commit | e94d843e8b2772ec860258f006c8a3126a92a781 (patch) | |
tree | 5d1268ac396b42855e332949d30030ad374c4666 | |
parent | 78dfe62633ce4fe6e6a70afae04168e1f102b673 (diff) | |
parent | e66e2e2b09c04acf733089658cf32a27708b8d16 (diff) | |
download | spike-e94d843e8b2772ec860258f006c8a3126a92a781.zip spike-e94d843e8b2772ec860258f006c8a3126a92a781.tar.gz spike-e94d843e8b2772ec860258f006c8a3126a92a781.tar.bz2 |
Merge pull request #997 from riscv-software-src/simplify-decode_insn
Simplify decode_insn and insn_desc_t
-rw-r--r-- | customext/cflush.cc | 6 | ||||
-rw-r--r-- | riscv/processor.cc | 23 | ||||
-rw-r--r-- | riscv/processor.h | 6 | ||||
-rw-r--r-- | riscv/rocc.cc | 8 |
4 files changed, 21 insertions, 22 deletions
diff --git a/customext/cflush.cc b/customext/cflush.cc index 1a5cfa2..8b72a97 100644 --- a/customext/cflush.cc +++ b/customext/cflush.cc @@ -24,9 +24,9 @@ class cflush_t : public extension_t std::vector<insn_desc_t> get_instructions() { std::vector<insn_desc_t> insns; - insns.push_back((insn_desc_t){true, 0xFC000073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); - insns.push_back((insn_desc_t){true, 0xFC200073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); - insns.push_back((insn_desc_t){true, 0xFC100073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); + insns.push_back((insn_desc_t){0xFC000073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); + insns.push_back((insn_desc_t){0xFC200073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); + insns.push_back((insn_desc_t){0xFC100073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); return insns; } diff --git a/riscv/processor.cc b/riscv/processor.cc index 661058c..a9003a8 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -885,11 +885,11 @@ insn_func_t processor_t::decode_insn(insn_t insn) bool rve = extension_enabled('E'); - if (unlikely(insn.bits() != desc.match || !desc.func(xlen, rve))) { + if (unlikely(insn.bits() != desc.match)) { // fall back to linear search int cnt = 0; insn_desc_t* p = &instructions[0]; - while ((insn.bits() & p->mask) != p->match || !desc.func(xlen, rve)) + while ((insn.bits() & p->mask) != p->match) p++, cnt++; desc = *p; @@ -911,6 +911,8 @@ insn_func_t processor_t::decode_insn(insn_t insn) void processor_t::register_insn(insn_desc_t desc) { + assert(desc.rv32i && desc.rv64i && desc.rv32e && desc.rv64e); + instructions.push_back(desc); } @@ -963,14 +965,15 @@ void processor_t::register_base_instructions() extern reg_t rv64i_##name(processor_t*, insn_t, reg_t); \ extern reg_t rv32e_##name(processor_t*, insn_t, reg_t); \ extern reg_t rv64e_##name(processor_t*, insn_t, reg_t); \ - register_insn((insn_desc_t) { \ - name##_supported, \ - name##_match, \ - name##_mask, \ - rv32i_##name, \ - rv64i_##name, \ - rv32e_##name, \ - rv64e_##name}); + if (name##_supported) { \ + register_insn((insn_desc_t) { \ + name##_match, \ + name##_mask, \ + rv32i_##name, \ + rv64i_##name, \ + rv32e_##name, \ + rv64e_##name}); \ + } #include "insn_list.h" #undef DEFINE_INSN diff --git a/riscv/processor.h b/riscv/processor.h index 96fdc54..ec1b400 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -29,7 +29,6 @@ reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc); struct insn_desc_t { - bool supported; insn_bits_t match; insn_bits_t mask; insn_func_t rv32i; @@ -39,9 +38,6 @@ struct insn_desc_t insn_func_t func(int xlen, bool rve) { - if (!supported) - return NULL; - if (rve) return xlen == 64 ? rv64e : rv32e; else @@ -50,7 +46,7 @@ struct insn_desc_t static insn_desc_t illegal() { - return {true, 0, 0, &illegal_instruction, &illegal_instruction, &illegal_instruction, &illegal_instruction}; + return {0, 0, &illegal_instruction, &illegal_instruction, &illegal_instruction, &illegal_instruction}; } }; diff --git a/riscv/rocc.cc b/riscv/rocc.cc index 2d09095..f50934f 100644 --- a/riscv/rocc.cc +++ b/riscv/rocc.cc @@ -32,10 +32,10 @@ customX(3) std::vector<insn_desc_t> rocc_t::get_instructions() { std::vector<insn_desc_t> insns; - insns.push_back((insn_desc_t){true, 0x0b, 0x7f, &::illegal_instruction, c0, &::illegal_instruction, c0}); - insns.push_back((insn_desc_t){true, 0x2b, 0x7f, &::illegal_instruction, c1, &::illegal_instruction, c1}); - insns.push_back((insn_desc_t){true, 0x5b, 0x7f, &::illegal_instruction, c2, &::illegal_instruction, c2}); - insns.push_back((insn_desc_t){true, 0x7b, 0x7f, &::illegal_instruction, c3, &::illegal_instruction, c3}); + insns.push_back((insn_desc_t){0x0b, 0x7f, &::illegal_instruction, c0, &::illegal_instruction, c0}); + insns.push_back((insn_desc_t){0x2b, 0x7f, &::illegal_instruction, c1, &::illegal_instruction, c1}); + insns.push_back((insn_desc_t){0x5b, 0x7f, &::illegal_instruction, c2, &::illegal_instruction, c2}); + insns.push_back((insn_desc_t){0x7b, 0x7f, &::illegal_instruction, c3, &::illegal_instruction, c3}); return insns; } |