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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-27 00:42:12 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-28 22:36:14 -0700 |
commit | d4f881d0ecce46c6f011603aeb74ad3a72b28fbf (patch) | |
tree | 1b28dbd6172bc8e9b87c4652890b4e101e95e67a | |
parent | 92d41ccbc02ed848d89ae4ed61be42730aa02140 (diff) | |
download | spike-d4f881d0ecce46c6f011603aeb74ad3a72b28fbf.zip spike-d4f881d0ecce46c6f011603aeb74ad3a72b28fbf.tar.gz spike-d4f881d0ecce46c6f011603aeb74ad3a72b28fbf.tar.bz2 |
rvv: wrap align and overlap checking macro
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
-rw-r--r-- | riscv/decode.h | 35 | ||||
-rw-r--r-- | riscv/insns/vl1r_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vmvnfr_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vs1r_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vsetvl.h | 2 | ||||
-rw-r--r-- | riscv/insns/vsetvli.h | 2 |
6 files changed, 36 insertions, 9 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index ad35e98..9507882 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -112,12 +112,21 @@ public: uint64_t rvc_rs2s() { return 8 + x(2, 3); } uint64_t v_vm() { return x(25, 1); } + uint64_t v_wd() { return x(26, 1); } uint64_t v_nf() { return x(29, 3); } uint64_t v_simm5() { return xs(15, 5); } uint64_t v_zimm5() { return x(15, 5); } uint64_t v_zimm11() { return x(20, 11); } - uint64_t v_lmul() { return 1 << x(20, 2); } + uint64_t v_lmul() { return x(20, 2); } uint64_t v_sew() { return 1 << (x(22, 3) + 3); } + uint64_t v_frac_lmul() { return x(25, 1); } + uint64_t v_width() { return x(12, 3); } + uint64_t v_mop() { return x(26, 2); } + uint64_t v_lumop() { return x(20, 5); } + uint64_t v_sumop() { return x(20, 5); } + uint64_t v_vta() { return x(26, 1); } + uint64_t v_vma() { return x(27, 1); } + uint64_t v_mew() { return x(28, 1); } private: insn_bits_t b; @@ -236,12 +245,18 @@ private: WRITE_VSTATUS; \ dirty_vs_state; \ } while (0); -#define require_vector_for_vsetvl \ +#define require_vector_novtype(is_log) \ do { \ require_vector_vs; \ require_extension('V'); \ + if (is_log) \ + WRITE_VSTATUS; \ dirty_vs_state; \ } while (0); +#define require_align(val, pos) require(is_aligned(val, pos)) +#define require_noover(astart, asize, bstart, bsize) \ + require(!is_overlapped(astart, asize, bstart, bsize)) +#define require_vm do { if (insn.v_vm() == 0) require(insn.rd() != 0);} while(0); #define set_fp_exceptions ({ if (softfloat_exceptionFlags) { \ dirty_fp_state; \ @@ -350,6 +365,9 @@ inline long double to_f(float128_t f){long double r; memcpy(&r, &f, sizeof(r)); #define e32 32 // 32b elements #define e64 64 // 64b elements #define e128 128 // 128b elements +#define e256 256 // 256b elements +#define e512 512 // 512b elements +#define e1024 1024 // 1024b elements #define vsext(x, sew) (((sreg_t)(x) << (64-sew)) >> (64-sew)) #define vzext(x, sew) (((reg_t)(x) << (64-sew)) >> (64-sew)) @@ -401,14 +419,23 @@ inline long double to_f(float128_t f){long double r; memcpy(&r, &f, sizeof(r)); // // vector: operation and register acccess check helper // -static inline bool is_overlapped(const int astart, const int asize, - const int bstart, const int bsize) +static inline bool is_overlapped(const int astart, int asize, + const int bstart, int bsize) { + asize = asize == 0 ? 1 : asize; + bsize = bsize == 0 ? 1 : bsize; + const int aend = astart + asize; const int bend = bstart + bsize; + return std::max(aend, bend) - std::min(astart, bstart) < asize + bsize; } +static inline bool is_aligned(const unsigned val, const unsigned pos) +{ + return pos ? (val & (pos - 1)) == 0 : true; +} + #define VI_NARROW_CHECK_COMMON \ require_vector;\ require(P.VU.vlmul <= 4); \ diff --git a/riscv/insns/vl1r_v.h b/riscv/insns/vl1r_v.h index 09f4040..61e8765 100644 --- a/riscv/insns/vl1r_v.h +++ b/riscv/insns/vl1r_v.h @@ -1,5 +1,5 @@ // vl1r.v vd, (rs1) -require_vector; +require_vector_novtype(true); const reg_t baseAddr = RS1; const reg_t vd = insn.rd(); for (reg_t i = 0; i < P.VU.vlenb; ++i) { diff --git a/riscv/insns/vmvnfr_v.h b/riscv/insns/vmvnfr_v.h index bafcb4d..51045ce 100644 --- a/riscv/insns/vmvnfr_v.h +++ b/riscv/insns/vmvnfr_v.h @@ -1,5 +1,5 @@ // vmv1r.v vd, vs2 -require_vector; +require_vector_novtype(true); const reg_t baseAddr = RS1; const reg_t vd = insn.rd(); const reg_t vs2 = insn.rs2(); diff --git a/riscv/insns/vs1r_v.h b/riscv/insns/vs1r_v.h index c176a20..072664c 100644 --- a/riscv/insns/vs1r_v.h +++ b/riscv/insns/vs1r_v.h @@ -1,5 +1,5 @@ // vs1r.v vs3, (rs1) -require_vector; +require_vector_novtype(true); const reg_t baseAddr = RS1; const reg_t vs3 = insn.rd(); for (reg_t i = 0; i < P.VU.vlenb; ++i) { diff --git a/riscv/insns/vsetvl.h b/riscv/insns/vsetvl.h index fb3a558..4d03542 100644 --- a/riscv/insns/vsetvl.h +++ b/riscv/insns/vsetvl.h @@ -1,2 +1,2 @@ -require_vector_for_vsetvl; +require_vector_novtype(false); WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, RS2)); diff --git a/riscv/insns/vsetvli.h b/riscv/insns/vsetvli.h index 56d3a9a..d1f43b5 100644 --- a/riscv/insns/vsetvli.h +++ b/riscv/insns/vsetvli.h @@ -1,2 +1,2 @@ -require_vector_for_vsetvl; +require_vector_novtype(false); WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, insn.v_zimm11())); |