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author | Tim Newsome <tim@sifive.com> | 2022-03-24 11:22:33 -0700 |
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committer | Tim Newsome <tim@sifive.com> | 2022-04-05 10:33:31 -0700 |
commit | 972943662c6e608e5d321c9128cdb9aaf903a4ae (patch) | |
tree | 8413a0780d5de48576d2a128878b7177eefe407d | |
parent | f3d14f936965fb48a140ab010a9e1b0b2908bf2d (diff) | |
download | spike-972943662c6e608e5d321c9128cdb9aaf903a4ae.zip spike-972943662c6e608e5d321c9128cdb9aaf903a4ae.tar.gz spike-972943662c6e608e5d321c9128cdb9aaf903a4ae.tar.bz2 |
Don't access triggers vector directly from csrs.cc.
-rw-r--r-- | riscv/csrs.cc | 8 | ||||
-rw-r--r-- | riscv/triggers.cc | 20 | ||||
-rw-r--r-- | riscv/triggers.h | 5 |
3 files changed, 29 insertions, 4 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 69e3c4b..aa726d4 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -991,11 +991,11 @@ tdata1_csr_t::tdata1_csr_t(processor_t* const proc, const reg_t addr): } reg_t tdata1_csr_t::read() const noexcept { - return proc->TM.triggers[state->tselect->read()]->tdata1_read(proc); + return proc->TM.tdata1_read(proc, state->tselect->read()); } bool tdata1_csr_t::unlogged_write(const reg_t val) noexcept { - return proc->TM.triggers[state->tselect->read()]->tdata1_write(proc, val); + return proc->TM.tdata1_write(proc, state->tselect->read(), val); } @@ -1004,11 +1004,11 @@ tdata2_csr_t::tdata2_csr_t(processor_t* const proc, const reg_t addr): } reg_t tdata2_csr_t::read() const noexcept { - return proc->TM.triggers[state->tselect->read()]->tdata2_read(proc); + return proc->TM.tdata2_read(proc, state->tselect->read()); } bool tdata2_csr_t::unlogged_write(const reg_t val) noexcept { - return proc->TM.triggers[state->tselect->read()]->tdata2_write(proc, val); + return proc->TM.tdata2_write(proc, state->tselect->read(), val); } diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 5b9d853..2cb4b13 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -173,5 +173,25 @@ match_result_t module_t::memory_access_match(action_t *action, operation_t opera return MATCH_NONE; } +reg_t module_t::tdata1_read(const processor_t *proc, unsigned index) const noexcept +{ + return triggers[index]->tdata1_read(proc); +} + +bool module_t::tdata1_write(processor_t *proc, unsigned index, const reg_t val) noexcept +{ + return triggers[index]->tdata1_write(proc, val); +} + +reg_t module_t::tdata2_read(const processor_t *proc, unsigned index) const noexcept +{ + return triggers[index]->tdata2_read(proc); +} + +bool module_t::tdata2_write(processor_t *proc, unsigned index, const reg_t val) noexcept +{ + return triggers[index]->tdata2_write(proc, val); +} + }; diff --git a/riscv/triggers.h b/riscv/triggers.h index 41bff75..bcd4b01 100644 --- a/riscv/triggers.h +++ b/riscv/triggers.h @@ -103,6 +103,11 @@ public: match_result_t memory_access_match(action_t *action, operation_t operation, reg_t address, reg_t data); + reg_t tdata1_read(const processor_t *proc, unsigned index) const noexcept; + bool tdata1_write(processor_t *proc, unsigned index, const reg_t val) noexcept; + reg_t tdata2_read(const processor_t *proc, unsigned index) const noexcept; + bool tdata2_write(processor_t *proc, unsigned index, const reg_t val) noexcept; + processor_t *proc; std::vector<mcontrol_t *> triggers; }; |