diff options
author | Ryan Buchner <ryan.buchner@arilinc.com> | 2022-04-21 11:35:26 -0700 |
---|---|---|
committer | Ryan Buchner <ryan.buchner@arilinc.com> | 2022-04-21 13:00:07 -0700 |
commit | 8948aef6dcad90fd80d6b8267e2fc2eeb4163a64 (patch) | |
tree | 93d0087c6e6343a91f034d13c51227c9e8aae337 | |
parent | 61eba540e15d4f27d8c3a78b605c614096b3e552 (diff) | |
download | spike-8948aef6dcad90fd80d6b8267e2fc2eeb4163a64.zip spike-8948aef6dcad90fd80d6b8267e2fc2eeb4163a64.tar.gz spike-8948aef6dcad90fd80d6b8267e2fc2eeb4163a64.tar.bz2 |
Add actually_store tag to misaligned_store function
Is passed along to the contained store_func.
-rw-r--r-- | riscv/mmu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 415cf1a..bb4c27e 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -65,11 +65,11 @@ public: #endif } - inline void misaligned_store(reg_t addr, reg_t data, size_t size, uint32_t xlate_flags) + inline void misaligned_store(reg_t addr, reg_t data, size_t size, uint32_t xlate_flags, bool actually_store=true) { #ifdef RISCV_ENABLE_MISALIGNED for (size_t i = 0; i < size; i++) - store_uint8(addr + (target_big_endian? size-1-i : i), data >> (i * 8)); + store_uint8(addr + (target_big_endian? size-1-i : i), data >> (i * 8), actually_store); #else bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_VIRT & xlate_flags); throw trap_store_address_misaligned(gva, addr, 0, 0); |