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| author | Scott Johnson <scott.johnson@arilinc.com> | 2022-08-29 08:32:41 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-08-29 08:32:41 -0700 |
| commit | 7f2f73609bcc3a06205abc0859c36f231d5bccfb (patch) | |
| tree | a9eda1089ea2580fbe6195a8963c4073045a9155 | |
| parent | f1c5178f2c559c2c6281f10d46c410c684fe41de (diff) | |
| parent | 3ac734e195e76e7c5e52448a95ea91885af31647 (diff) | |
| download | spike-7f2f73609bcc3a06205abc0859c36f231d5bccfb.zip spike-7f2f73609bcc3a06205abc0859c36f231d5bccfb.tar.gz spike-7f2f73609bcc3a06205abc0859c36f231d5bccfb.tar.bz2 | |
Merge pull request #1074 from YenHaoChen/master
Fix tval on illegal instruction faults with long illegal instruction
| -rw-r--r-- | riscv/processor.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 620a6f4..3d56abc 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -949,7 +949,10 @@ reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek) reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc) { - throw trap_illegal_instruction(insn.bits()); + // The illegal instruction can be longer than ILEN bits, where the tval will + // contain the first ILEN bits of the faulting instruction. We hard-code the + // ILEN to 32 bits since all official instructions have at most 32 bits. + throw trap_illegal_instruction(insn.bits() & 0xffffffffULL); } insn_func_t processor_t::decode_insn(insn_t insn) |