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authorAndrew Waterman <andrew@sifive.com>2022-06-06 20:36:05 -0700
committerAndrew Waterman <andrew@sifive.com>2022-06-06 20:54:17 -0700
commit7d943d740afb6a42b50c979800608c6fb1614d0c (patch)
treee92f3f4934f50ad1f8957441dd026a275d8d75b9
parentd2020b3256cf9a832cbbfe7a32c5753abe75cb7d (diff)
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Don't mask instruction bits
No longer needed, since they are no longer sign-extended. Fixes #1022 by eliminating undefined behavior (64-bit instructions resulted in a shift amount equal to the datatype width).
-rw-r--r--riscv/decode.h2
-rw-r--r--riscv/processor.cc2
2 files changed, 2 insertions, 2 deletions
diff --git a/riscv/decode.h b/riscv/decode.h
index d56d496..72b4a6b 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -79,7 +79,7 @@ class insn_t
public:
insn_t() = default;
insn_t(insn_bits_t bits) : b(bits) {}
- insn_bits_t bits() { return b & ~((UINT64_MAX) << (length() * 8)); }
+ insn_bits_t bits() { return b; }
int length() { return insn_length(b); }
int64_t i_imm() { return xs(20, 12); }
int64_t shamt() { return x(20, 6); }
diff --git a/riscv/processor.cc b/riscv/processor.cc
index bb41248..c4ca0bc 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -796,7 +796,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
void processor_t::disasm(insn_t insn)
{
- uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
+ uint64_t bits = insn.bits();
if (last_pc != state.pc || last_bits != bits) {
std::stringstream s; // first put everything in a string, later send it to output