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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-08-03 00:06:39 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-08-03 21:57:26 -0700 |
| commit | 7775c6fb7cc1b29bf529fee9fb900cef513222c1 (patch) | |
| tree | e5ff08c8b1b55aaa3b347532b80145e7875c9099 | |
| parent | f5e4f0cf329c13a9dea4bbc36c535572186e9c41 (diff) | |
| download | spike-7775c6fb7cc1b29bf529fee9fb900cef513222c1.zip spike-7775c6fb7cc1b29bf529fee9fb900cef513222c1.tar.gz spike-7775c6fb7cc1b29bf529fee9fb900cef513222c1.tar.bz2 | |
op: hyperviosr: fix exception code and name
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/encoding.h | 6 | ||||
| -rw-r--r-- | riscv/insns/ecall.h | 4 | ||||
| -rw-r--r-- | riscv/trap.h | 2 |
3 files changed, 6 insertions, 6 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index 1ad6ec2..f621db3 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -2128,8 +2128,8 @@ #define CAUSE_MISALIGNED_STORE 0x6 #define CAUSE_STORE_ACCESS 0x7 #define CAUSE_USER_ECALL 0x8 -#define CAUSE_HYPERVISOR_ECALL 0x9 -#define CAUSE_SUPERVISOR_ECALL 0xa +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa #define CAUSE_MACHINE_ECALL 0xb #define CAUSE_FETCH_PAGE_FAULT 0xc #define CAUSE_LOAD_PAGE_FAULT 0xd @@ -3211,8 +3211,8 @@ DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) -DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("virtual_supervisor_ecall", CAUSE_VIRTUAL_SUPERVISOR_ECALL) DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) diff --git a/riscv/insns/ecall.h b/riscv/insns/ecall.h index f5a064b..e6c723f 100644 --- a/riscv/insns/ecall.h +++ b/riscv/insns/ecall.h @@ -3,9 +3,9 @@ switch (STATE.prv) case PRV_U: throw trap_user_ecall(); case PRV_S: if (STATE.v) - throw trap_supervisor_ecall(); + throw trap_virtual_supervisor_ecall(); else - throw trap_hypervisor_ecall(); + throw trap_supervisor_ecall(); case PRV_M: throw trap_machine_ecall(); default: abort(); } diff --git a/riscv/trap.h b/riscv/trap.h index 824af6f..4431d8a 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -82,7 +82,7 @@ DECLARE_MEM_TRAP(CAUSE_LOAD_ACCESS, load_access_fault) DECLARE_MEM_TRAP(CAUSE_STORE_ACCESS, store_access_fault) DECLARE_TRAP(CAUSE_USER_ECALL, user_ecall) DECLARE_TRAP(CAUSE_SUPERVISOR_ECALL, supervisor_ecall) -DECLARE_TRAP(CAUSE_HYPERVISOR_ECALL, hypervisor_ecall) +DECLARE_TRAP(CAUSE_VIRTUAL_SUPERVISOR_ECALL, virtual_supervisor_ecall) DECLARE_TRAP(CAUSE_MACHINE_ECALL, machine_ecall) DECLARE_MEM_TRAP(CAUSE_FETCH_PAGE_FAULT, instruction_page_fault) DECLARE_MEM_TRAP(CAUSE_LOAD_PAGE_FAULT, load_page_fault) |