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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-05 17:21:09 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-09 15:45:18 +0800 |
| commit | 6cca5ec9c566301f8e85f83c4505e53b1ffe9249 (patch) | |
| tree | d3b603d87ab19a32542e83b16d82b740a513e3a7 | |
| parent | ba10686fd18f3fbb036ca04b906deb57e7d1fe54 (diff) | |
| download | spike-6cca5ec9c566301f8e85f83c4505e53b1ffe9249.zip spike-6cca5ec9c566301f8e85f83c4505e53b1ffe9249.tar.gz spike-6cca5ec9c566301f8e85f83c4505e53b1ffe9249.tar.bz2 | |
modify take_interrupt to support LCOFIP irq
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 7cac387..164ecff 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -716,6 +716,8 @@ void processor_t::take_interrupt(reg_t pending_interrupts) enabled_interrupts = MIP_SSIP; else if (enabled_interrupts & MIP_STIP) enabled_interrupts = MIP_STIP; + else if (enabled_interrupts & MIP_LCOFIP) + enabled_interrupts = MIP_LCOFIP; else if (enabled_interrupts & MIP_VSEIP) enabled_interrupts = MIP_VSEIP; else if (enabled_interrupts & MIP_VSSIP) |