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author | liweiwei <liweiwei@iscas.ac.cn> | 2021-12-27 11:00:27 +0800 |
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committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-01-29 17:22:33 +0800 |
commit | 42cbf10dc1f6c6ce0a9591a53be2555f75da6c87 (patch) | |
tree | 8953ce7e6a245a277faf08d0b8cdab46133de7b8 | |
parent | 4557eef7005d648953ec00210c84cc234e1dd1eb (diff) | |
download | spike-42cbf10dc1f6c6ce0a9591a53be2555f75da6c87.zip spike-42cbf10dc1f6c6ce0a9591a53be2555f75da6c87.tar.gz spike-42cbf10dc1f6c6ce0a9591a53be2555f75da6c87.tar.bz2 |
add blocksz parameter to specify the cache block size for CBO operations
-rw-r--r-- | riscv/mmu.h | 6 | ||||
-rw-r--r-- | spike_main/spike.cc | 10 |
2 files changed, 16 insertions, 0 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 0b86f6c..af11078 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -389,12 +389,18 @@ public: return target_big_endian? target_endian<T>::to_be(n) : target_endian<T>::to_le(n); } + void set_cache_blocksz(uint64_t size) + { + blocksz = size; + } + private: simif_t* sim; processor_t* proc; memtracer_list_t tracer; reg_t load_reservation_address; uint16_t fetch_temp; + uint64_t blocksz; // implement an instruction cache for simulator performance icache_entry_t icache[ICACHE_ENTRIES]; diff --git a/spike_main/spike.cc b/spike_main/spike.cc index e2680cc..05619a7 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -72,6 +72,7 @@ static void help(int exit_code = 1) fprintf(stderr, " --dm-no-abstract-csr Debug module won't support abstract to authenticate\n"); fprintf(stderr, " --dm-no-halt-groups Debug module won't support halt groups\n"); fprintf(stderr, " --dm-no-impebreak Debug module won't support implicit ebreak in program buffer\n"); + fprintf(stderr, " --blocksz=<size> Cache block size (B) for CMO operations(powers of 2) [default 16]\n"); exit(exit_code); } @@ -241,6 +242,7 @@ int main(int argc, char** argv) uint16_t rbb_port = 0; bool use_rbb = false; unsigned dmi_rti = 0; + reg_t blocksz = 64; debug_module_config_t dm_config = { .progbufsize = 2, .max_sba_data_width = 0, @@ -376,6 +378,13 @@ int main(int argc, char** argv) exit(-1); } }); + parser.option(0, "blocksz", 1, [&](const char* s){ + blocksz = strtoull(s, 0, 0); + if (((blocksz & (blocksz - 1))) != 0) { + fprintf(stderr, "--blocksz should be power of 2\n"); + exit(-1); + } + }); auto argv1 = parser.parse(argv); std::vector<std::string> htif_args(argv1, (const char*const*)argv + argc); @@ -464,6 +473,7 @@ int main(int argc, char** argv) if (dc) s.get_core(i)->get_mmu()->register_memtracer(&*dc); for (auto e : extensions) s.get_core(i)->register_extension(e()); + s.get_core(i)->get_mmu()->set_cache_blocksz(blocksz); } s.set_debug(debug); |