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authorAndrew Waterman <waterman@cs.berkeley.edu>2013-03-25 22:50:37 -0700
committerAndrew Waterman <waterman@cs.berkeley.edu>2013-03-25 22:50:37 -0700
commit28ac3dbd81ee2f7e29944a40507c5fb9843e1e9a (patch)
treef922002cac71225f616d522878312ad444b4b440
parent41ba91339e2a40b0784f99927cd6b73690e3a725 (diff)
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add BSD license
-rw-r--r--LICENSE24
-rw-r--r--riscv/cachesim.cc2
-rw-r--r--riscv/cachesim.h2
-rw-r--r--riscv/common.h2
-rw-r--r--riscv/decode.h2
-rw-r--r--riscv/disasm.cc2
-rw-r--r--riscv/disasm.h2
-rw-r--r--riscv/htif.cc2
-rw-r--r--riscv/htif.h2
-rw-r--r--riscv/insn_header.h2
-rw-r--r--riscv/interactive.cc2
-rw-r--r--riscv/memtracer.h2
-rw-r--r--riscv/mmu.cc2
-rw-r--r--riscv/mmu.h2
-rw-r--r--riscv/opcodes.h2
-rw-r--r--riscv/pcr.h2
-rw-r--r--riscv/processor.cc2
-rw-r--r--riscv/processor.h2
-rw-r--r--riscv/riscv-isa-run.cc2
-rw-r--r--riscv/sim.cc2
-rw-r--r--riscv/sim.h2
-rw-r--r--riscv/trap.cc2
-rw-r--r--riscv/trap.h2
23 files changed, 68 insertions, 0 deletions
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 0000000..53e0e66
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,24 @@
+Copyright (c) 2013, The Regents of the University of California (Regents).
+All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+3. Neither the name of the Regents nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
+SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
+BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
+HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
+MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
diff --git a/riscv/cachesim.cc b/riscv/cachesim.cc
index cd33ca1..9a11187 100644
--- a/riscv/cachesim.cc
+++ b/riscv/cachesim.cc
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#include "cachesim.h"
#include "common.h"
#include <cstdlib>
diff --git a/riscv/cachesim.h b/riscv/cachesim.h
index 96631a0..51044c3 100644
--- a/riscv/cachesim.h
+++ b/riscv/cachesim.h
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#ifndef _RISCV_CACHE_SIM_H
#define _RISCV_CACHE_SIM_H
diff --git a/riscv/common.h b/riscv/common.h
index 03f8c8e..8ddd984 100644
--- a/riscv/common.h
+++ b/riscv/common.h
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#ifndef _RISCV_COMMON_H
#define _RISCV_COMMON_H
diff --git a/riscv/decode.h b/riscv/decode.h
index b8a036b..bf16e72 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#ifndef _RISCV_DECODE_H
#define _RISCV_DECODE_H
diff --git a/riscv/disasm.cc b/riscv/disasm.cc
index 1252a38..c59a5da 100644
--- a/riscv/disasm.cc
+++ b/riscv/disasm.cc
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#include "disasm.h"
#include <string>
#include <vector>
diff --git a/riscv/disasm.h b/riscv/disasm.h
index 0b55948..ee6d919 100644
--- a/riscv/disasm.h
+++ b/riscv/disasm.h
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#ifndef _RISCV_DISASM_H
#define _RISCV_DISASM_H
diff --git a/riscv/htif.cc b/riscv/htif.cc
index 438d862..0512b6f 100644
--- a/riscv/htif.cc
+++ b/riscv/htif.cc
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#include "htif.h"
#include "sim.h"
#include <unistd.h>
diff --git a/riscv/htif.h b/riscv/htif.h
index 034743a..3e4a88d 100644
--- a/riscv/htif.h
+++ b/riscv/htif.h
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#ifndef _HTIF_H
#define _HTIF_H
diff --git a/riscv/insn_header.h b/riscv/insn_header.h
index 9ea3586..c5f1080 100644
--- a/riscv/insn_header.h
+++ b/riscv/insn_header.h
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#include "processor.h"
#include "config.h"
#include "sim.h"
diff --git a/riscv/interactive.cc b/riscv/interactive.cc
index 58a9066..3f02910 100644
--- a/riscv/interactive.cc
+++ b/riscv/interactive.cc
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#include "sim.h"
#include "htif.h"
#include <sys/mman.h>
diff --git a/riscv/memtracer.h b/riscv/memtracer.h
index 82c02b6..127a641 100644
--- a/riscv/memtracer.h
+++ b/riscv/memtracer.h
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#ifndef _MEMTRACER_H
#define _MEMTRACER_H
diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index 9f433b5..e95e5f9 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#include "mmu.h"
#include "sim.h"
#include "processor.h"
diff --git a/riscv/mmu.h b/riscv/mmu.h
index 58896ae..43a3ec9 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#ifndef _RISCV_MMU_H
#define _RISCV_MMU_H
diff --git a/riscv/opcodes.h b/riscv/opcodes.h
index 52af654..9ca7cc8 100644
--- a/riscv/opcodes.h
+++ b/riscv/opcodes.h
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
DECLARE_INSN(movn, 0x6f7, 0x1ffff)
DECLARE_INSN(vfsstw, 0x150f, 0x1ffff)
DECLARE_INSN(remuw, 0x7bb, 0x1ffff)
diff --git a/riscv/pcr.h b/riscv/pcr.h
index 33939d8..11bfc65 100644
--- a/riscv/pcr.h
+++ b/riscv/pcr.h
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#ifndef _RISCV_PCR_H
#define _RISCV_PCR_H
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 9f87f75..dbae921 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#include "processor.h"
#include "common.h"
#include "config.h"
diff --git a/riscv/processor.h b/riscv/processor.h
index 826fb96..e452df2 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#ifndef _RISCV_PROCESSOR_H
#define _RISCV_PROCESSOR_H
diff --git a/riscv/riscv-isa-run.cc b/riscv/riscv-isa-run.cc
index 852556c..142df33 100644
--- a/riscv/riscv-isa-run.cc
+++ b/riscv/riscv-isa-run.cc
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#include "sim.h"
#include "htif.h"
#include "cachesim.h"
diff --git a/riscv/sim.cc b/riscv/sim.cc
index 1cac94f..af51fea 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#include "sim.h"
#include "htif.h"
#include <sys/mman.h>
diff --git a/riscv/sim.h b/riscv/sim.h
index aed4e87..e3b4097 100644
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#ifndef _RISCV_SIM_H
#define _RISCV_SIM_H
diff --git a/riscv/trap.cc b/riscv/trap.cc
index d873a19..ba0d867 100644
--- a/riscv/trap.cc
+++ b/riscv/trap.cc
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#include "trap.h"
const char* trap_name(trap_t t)
diff --git a/riscv/trap.h b/riscv/trap.h
index d09da3f..6448e51 100644
--- a/riscv/trap.h
+++ b/riscv/trap.h
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
#ifndef _RISCV_TRAP_H
#define _RISCV_TRAP_H