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author | Andrew Waterman <andrew@sifive.com> | 2017-11-27 14:29:03 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2017-11-27 14:29:03 -0800 |
commit | 12714e371e9b8ce2efcf0e77347ed1b33c8de27b (patch) | |
tree | c0a5a34b643fd8be0303964ca0de3db1e3f6c339 | |
parent | a06091861c23d5154d750137f5ff3a819a9fa283 (diff) | |
download | spike-12714e371e9b8ce2efcf0e77347ed1b33c8de27b.zip spike-12714e371e9b8ce2efcf0e77347ed1b33c8de27b.tar.gz spike-12714e371e9b8ce2efcf0e77347ed1b33c8de27b.tar.bz2 |
Rename badaddr to tval
-rw-r--r-- | riscv/encoding.h | 8 | ||||
-rw-r--r-- | riscv/mmu.h | 4 | ||||
-rw-r--r-- | riscv/processor.cc | 18 | ||||
-rw-r--r-- | riscv/processor.h | 4 | ||||
-rw-r--r-- | riscv/trap.h | 16 |
5 files changed, 25 insertions, 25 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index 1173fe5..c109ce1 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -790,7 +790,7 @@ #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 -#define CSR_SBADADDR 0x143 +#define CSR_STVAL 0x143 #define CSR_SIP 0x144 #define CSR_SATP 0x180 #define CSR_MSTATUS 0x300 @@ -803,7 +803,7 @@ #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 #define CSR_MCAUSE 0x342 -#define CSR_MBADADDR 0x343 +#define CSR_MTVAL 0x343 #define CSR_MIP 0x344 #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 @@ -1282,7 +1282,7 @@ DECLARE_CSR(scounteren, CSR_SCOUNTEREN) DECLARE_CSR(sscratch, CSR_SSCRATCH) DECLARE_CSR(sepc, CSR_SEPC) DECLARE_CSR(scause, CSR_SCAUSE) -DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(stval, CSR_STVAL) DECLARE_CSR(sip, CSR_SIP) DECLARE_CSR(satp, CSR_SATP) DECLARE_CSR(mstatus, CSR_MSTATUS) @@ -1295,7 +1295,7 @@ DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) DECLARE_CSR(mscratch, CSR_MSCRATCH) DECLARE_CSR(mepc, CSR_MEPC) DECLARE_CSR(mcause, CSR_MCAUSE) -DECLARE_CSR(mbadaddr, CSR_MBADADDR) +DECLARE_CSR(mtval, CSR_MTVAL) DECLARE_CSR(mip, CSR_MIP) DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) diff --git a/riscv/mmu.h b/riscv/mmu.h index e39cd94..0b58f69 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -144,10 +144,10 @@ public: return lhs; \ } catch (trap_load_page_fault& t) { \ /* AMO faults should be reported as store faults */ \ - throw trap_store_page_fault(t.get_badaddr()); \ + throw trap_store_page_fault(t.get_tval()); \ } catch (trap_load_access_fault& t) { \ /* AMO faults should be reported as store faults */ \ - throw trap_store_access_fault(t.get_badaddr()); \ + throw trap_store_access_fault(t.get_tval()); \ } \ } diff --git a/riscv/processor.cc b/riscv/processor.cc index 5f095c3..516a708 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -239,9 +239,9 @@ void processor_t::take_trap(trap_t& t, reg_t epc) if (debug) { fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n", id, t.name(), epc); - if (t.has_badaddr()) - fprintf(stderr, "core %3d: badaddr 0x%016" PRIx64 "\n", id, - t.get_badaddr()); + if (t.has_tval()) + fprintf(stderr, "core %3d: tval 0x%016" PRIx64 "\n", id, + t.get_tval()); } if (state.dcsr.cause) { @@ -272,7 +272,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc) state.pc = state.stvec; state.scause = t.cause(); state.sepc = epc; - state.sbadaddr = t.get_badaddr(); + state.stval = t.get_tval(); reg_t s = state.mstatus; s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); @@ -285,7 +285,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc) state.pc = (state.mtvec & ~(reg_t)1) + vector; state.mepc = epc; state.mcause = t.cause(); - state.mbadaddr = t.get_badaddr(); + state.mtval = t.get_tval(); reg_t s = state.mstatus; s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); @@ -439,12 +439,12 @@ void processor_t::set_csr(int which, reg_t val) case CSR_STVEC: state.stvec = val >> 2 << 2; break; case CSR_SSCRATCH: state.sscratch = val; break; case CSR_SCAUSE: state.scause = val; break; - case CSR_SBADADDR: state.sbadaddr = val; break; + case CSR_STVAL: state.stval = val; break; case CSR_MEPC: state.mepc = val; break; case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break; case CSR_MSCRATCH: state.mscratch = val; break; case CSR_MCAUSE: state.mcause = val; break; - case CSR_MBADADDR: state.mbadaddr = val; break; + case CSR_MTVAL: state.mtval = val; break; case CSR_MISA: { if (!(val & (1L << ('F' - 'A')))) val &= ~(1L << ('D' - 'A')); @@ -584,7 +584,7 @@ reg_t processor_t::get_csr(int which) case CSR_SIP: return state.mip & state.mideleg; case CSR_SIE: return state.mie & state.mideleg; case CSR_SEPC: return state.sepc; - case CSR_SBADADDR: return state.sbadaddr; + case CSR_STVAL: return state.stval; case CSR_STVEC: return state.stvec; case CSR_SCAUSE: if (max_xlen > xlen) @@ -601,7 +601,7 @@ reg_t processor_t::get_csr(int which) case CSR_MEPC: return state.mepc; case CSR_MSCRATCH: return state.mscratch; case CSR_MCAUSE: return state.mcause; - case CSR_MBADADDR: return state.mbadaddr; + case CSR_MTVAL: return state.mtval; case CSR_MISA: return isa; case CSR_MARCHID: return 0; case CSR_MIMPID: return 0; diff --git a/riscv/processor.h b/riscv/processor.h index f37fb59..1b94b1f 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -97,7 +97,7 @@ struct state_t reg_t prv; // TODO: Can this be an enum instead? reg_t mstatus; reg_t mepc; - reg_t mbadaddr; + reg_t mtval; reg_t mscratch; reg_t mtvec; reg_t mcause; @@ -109,7 +109,7 @@ struct state_t uint32_t mcounteren; uint32_t scounteren; reg_t sepc; - reg_t sbadaddr; + reg_t stval; reg_t sscratch; reg_t stvec; reg_t satp; diff --git a/riscv/trap.h b/riscv/trap.h index 1fe44eb..b5b8a50 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -13,8 +13,8 @@ class trap_t public: trap_t(reg_t which) : which(which) {} virtual const char* name(); - virtual bool has_badaddr() { return false; } - virtual reg_t get_badaddr() { return 0; } + virtual bool has_tval() { return false; } + virtual reg_t get_tval() { return 0; } reg_t cause() { return which; } private: char _name[16]; @@ -24,12 +24,12 @@ class trap_t class mem_trap_t : public trap_t { public: - mem_trap_t(reg_t which, reg_t badaddr) - : trap_t(which), badaddr(badaddr) {} - bool has_badaddr() override { return true; } - reg_t get_badaddr() override { return badaddr; } + mem_trap_t(reg_t which, reg_t tval) + : trap_t(which), tval(tval) {} + bool has_tval() override { return true; } + reg_t get_tval() override { return tval; } private: - reg_t badaddr; + reg_t tval; }; #define DECLARE_TRAP(n, x) class trap_##x : public trap_t { \ @@ -40,7 +40,7 @@ class mem_trap_t : public trap_t #define DECLARE_MEM_TRAP(n, x) class trap_##x : public mem_trap_t { \ public: \ - trap_##x(reg_t badaddr) : mem_trap_t(n, badaddr) {} \ + trap_##x(reg_t tval) : mem_trap_t(n, tval) {} \ const char* name() { return "trap_"#x; } \ }; |