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| author | soberl@nvidia.com <soberl@nvidia.com> | 2022-05-03 19:51:33 -0700 |
|---|---|---|
| committer | soberl@nvidia.com <soberl@nvidia.com> | 2022-05-04 18:26:25 -0700 |
| commit | 115a9b3dc21aa001275ce898bc5bc73e43fccab5 (patch) | |
| tree | dba044a8be17de721d147b54d6277f591df51ca6 | |
| parent | af500657c3ecde57fb88ed027dbdaa5da72a1c4b (diff) | |
| download | spike-115a9b3dc21aa001275ce898bc5bc73e43fccab5.zip spike-115a9b3dc21aa001275ce898bc5bc73e43fccab5.tar.gz spike-115a9b3dc21aa001275ce898bc5bc73e43fccab5.tar.bz2 | |
Update mmu_t::pmp_ok() for ePMP in case matching region is not found
| -rw-r--r-- | riscv/mmu.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 1ef81cf..2918f0b 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -242,7 +242,11 @@ bool mmu_t::pmp_ok(reg_t addr, reg_t len, access_type type, reg_t mode) } } - return mode == PRV_M; + // in case matching region is not found + const bool mseccfg_mml = proc->state.mseccfg->get_mml(); + const bool mseccfg_mmwp = proc->state.mseccfg->get_mmwp(); + return ((mode == PRV_M) && !mseccfg_mmwp + && (!mseccfg_mml || ((type == LOAD) || (type == STORE)))); } reg_t mmu_t::pmp_homogeneous(reg_t addr, reg_t len) |