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author | Tim Newsome <tim@sifive.com> | 2022-03-15 08:52:32 -0700 |
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committer | Tim Newsome <tim@sifive.com> | 2022-03-30 10:41:44 -0700 |
commit | 08442c1aad70be858f177e277b02a340a22346ba (patch) | |
tree | ad04cfbbca29e1ca61dccfd3ea4ad88fdaf681de | |
parent | a2a2587426e57f6207d5389620e9109bc0f82e6b (diff) | |
download | spike-08442c1aad70be858f177e277b02a340a22346ba.zip spike-08442c1aad70be858f177e277b02a340a22346ba.tar.gz spike-08442c1aad70be858f177e277b02a340a22346ba.tar.bz2 |
mcontrol_action_t -> triggers::action_t
These actions are not specific to the mcontrol trigger.
-rw-r--r-- | riscv/csrs.cc | 2 | ||||
-rw-r--r-- | riscv/execute.cc | 4 | ||||
-rw-r--r-- | riscv/processor.h | 11 | ||||
-rw-r--r-- | riscv/triggers.h | 11 |
4 files changed, 15 insertions, 13 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index a34bfff..2ca9689 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1021,7 +1021,7 @@ bool tdata1_csr_t::unlogged_write(const reg_t val) noexcept { mc->dmode = get_field(val, MCONTROL_DMODE(xlen)); mc->select = get_field(val, MCONTROL_SELECT); mc->timing = get_field(val, MCONTROL_TIMING); - mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION); + mc->action = (triggers::action_t) get_field(val, MCONTROL_ACTION); mc->chain = get_field(val, MCONTROL_CHAIN); mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH); mc->m = get_field(val, MCONTROL_M); diff --git a/riscv/execute.cc b/riscv/execute.cc index 72ffa27..212f273 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -325,10 +325,10 @@ void processor_t::step(size_t n) mmu->matched_trigger = NULL; } switch (state.mcontrol[t.index].action) { - case ACTION_DEBUG_MODE: + case triggers::ACTION_DEBUG_MODE: enter_debug_mode(DCSR_CAUSE_HWBP); break; - case ACTION_DEBUG_EXCEPTION: { + case triggers::ACTION_DEBUG_EXCEPTION: { trap_breakpoint trap(state.v, t.address); take_trap(trap, pc); break; diff --git a/riscv/processor.h b/riscv/processor.h index 1b5c818..3e06d5b 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -58,15 +58,6 @@ typedef std::vector<std::tuple<reg_t, uint64_t, uint8_t>> commit_log_mem_t; typedef enum { - ACTION_DEBUG_EXCEPTION = MCONTROL_ACTION_DEBUG_EXCEPTION, - ACTION_DEBUG_MODE = MCONTROL_ACTION_DEBUG_MODE, - ACTION_TRACE_START = MCONTROL_ACTION_TRACE_START, - ACTION_TRACE_STOP = MCONTROL_ACTION_TRACE_STOP, - ACTION_TRACE_EMIT = MCONTROL_ACTION_TRACE_EMIT -} mcontrol_action_t; - -typedef enum -{ MATCH_EQUAL = MCONTROL_MATCH_EQUAL, MATCH_NAPOT = MCONTROL_MATCH_NAPOT, MATCH_GE = MCONTROL_MATCH_GE, @@ -82,7 +73,7 @@ typedef struct uint8_t maskmax; bool select; bool timing; - mcontrol_action_t action; + triggers::action_t action; bool chain; mcontrol_match_t match; bool m; diff --git a/riscv/triggers.h b/riscv/triggers.h index 6784a6c..068acb9 100644 --- a/riscv/triggers.h +++ b/riscv/triggers.h @@ -1,6 +1,8 @@ #ifndef _RISCV_TRIGGERS_H #define _RISCV_TRIGGERS_H +#include "decode.h" + namespace triggers { typedef enum { @@ -9,6 +11,15 @@ typedef enum { OPERATION_LOAD, } operation_t; +typedef enum +{ + ACTION_DEBUG_EXCEPTION = MCONTROL_ACTION_DEBUG_EXCEPTION, + ACTION_DEBUG_MODE = MCONTROL_ACTION_DEBUG_MODE, + ACTION_TRACE_START = MCONTROL_ACTION_TRACE_START, + ACTION_TRACE_STOP = MCONTROL_ACTION_TRACE_STOP, + ACTION_TRACE_EMIT = MCONTROL_ACTION_TRACE_EMIT +} action_t; + }; #endif |