In triggers, use optional<data> instead of {has_data, data}

4 files changed, 17 insertions, 16 deletions

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index 53c6fba..c77b6b1 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -76,7 +76,7 @@ reg_t mmu_t::translate(reg_t addr, reg_t len, access_type type, uint32_t xlate_f
 
 tlb_entry_t mmu_t::fetch_slow_path(reg_t vaddr)
 {
-  check_triggers(triggers::OPERATION_EXECUTE, vaddr, false);
+  check_triggers(triggers::OPERATION_EXECUTE, vaddr);
 
   tlb_entry_t result;
   reg_t vpn = vaddr >> PGSHIFT;
@@ -93,7 +93,7 @@ tlb_entry_t mmu_t::fetch_slow_path(reg_t vaddr)
     result = tlb_data[vpn % TLB_ENTRIES];
   }
 
-  check_triggers(triggers::OPERATION_EXECUTE, vaddr, true, from_le(*(const uint16_t*)(result.host_offset + vaddr)));
+  check_triggers(triggers::OPERATION_EXECUTE, vaddr, from_le(*(const uint16_t*)(result.host_offset + vaddr)));
 
   return result;
 }
@@ -149,13 +149,13 @@ bool mmu_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
   return sim->mmio_store(addr, len, bytes);
 }
 
-void mmu_t::check_triggers(triggers::operation_t operation, reg_t address, bool has_data, reg_t data)
+void mmu_t::check_triggers(triggers::operation_t operation, reg_t address, std::optional<reg_t> data)
 {
   if (matched_trigger || !proc)
     return;
 
   triggers::action_t action;
-  auto match = proc->TM.memory_access_match(&action, operation, address, has_data, data);
+  auto match = proc->TM.memory_access_match(&action, operation, address, data);
 
   switch (match) {
     case triggers::MATCH_NONE:
@@ -197,7 +197,7 @@ void mmu_t::load_slow_path_intrapage(reg_t addr, reg_t len, uint8_t* bytes, uint
 
 void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate_flags, bool UNUSED require_alignment)
 {
-  check_triggers(triggers::OPERATION_LOAD, addr, false);
+  check_triggers(triggers::OPERATION_LOAD, addr);
 
   if ((addr & (len - 1)) == 0) {
     load_slow_path_intrapage(addr, len, bytes, xlate_flags);
@@ -216,7 +216,7 @@ void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate
 #endif
   }
 
-  check_triggers(triggers::OPERATION_LOAD, addr, true, reg_from_bytes(len, bytes));
+  check_triggers(triggers::OPERATION_LOAD, addr, reg_from_bytes(len, bytes));
 }
 
 void mmu_t::store_slow_path_intrapage(reg_t addr, reg_t len, const uint8_t* bytes, uint32_t xlate_flags, bool actually_store)
@@ -246,7 +246,7 @@ void mmu_t::store_slow_path_intrapage(reg_t addr, reg_t len, const uint8_t* byte
 void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes, uint32_t xlate_flags, bool actually_store, bool UNUSED require_alignment)
 {
   if (actually_store)
-    check_triggers(triggers::OPERATION_STORE, addr, true, reg_from_bytes(len, bytes));
+    check_triggers(triggers::OPERATION_STORE, addr, reg_from_bytes(len, bytes));
 
   if (addr & (len - 1)) {
     bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_VIRT & xlate_flags);
diff --git a/riscv/mmu.h b/riscv/mmu.h
index 01e74ef..da84adc 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -387,7 +387,7 @@ private:
   bool mmio_load(reg_t addr, size_t len, uint8_t* bytes);
   bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes);
   bool mmio_ok(reg_t addr, access_type type);
-  void check_triggers(triggers::operation_t operation, reg_t address, bool has_data, reg_t data = 0);
+  void check_triggers(triggers::operation_t operation, reg_t address, std::optional<reg_t> data = std::nullopt);
   reg_t translate(reg_t addr, reg_t len, access_type type, uint32_t xlate_flags);
 
   // ITLB lookup
diff --git a/riscv/triggers.cc b/riscv/triggers.cc
index 5e2d1f6..90d9d54 100644
--- a/riscv/triggers.cc
+++ b/riscv/triggers.cc
@@ -101,7 +101,7 @@ bool mcontrol_t::simple_match(unsigned xlen, reg_t value) const {
   assert(0);
 }
 
-match_result_t mcontrol_t::memory_access_match(processor_t * const proc, operation_t operation, reg_t address, bool has_data, reg_t data) {
+match_result_t mcontrol_t::memory_access_match(processor_t * const proc, operation_t operation, reg_t address, std::optional<reg_t> data) {
   state_t * const state = proc->get_state();
   if ((operation == triggers::OPERATION_EXECUTE && !execute_bit) ||
       (operation == triggers::OPERATION_STORE && !store_bit) ||
@@ -114,9 +114,9 @@ match_result_t mcontrol_t::memory_access_match(processor_t * const proc, operati
 
   reg_t value;
   if (select) {
-    value = data;
-    if (!has_data)
+    if (!data.has_value())
       return MATCH_NONE;
+    value = *data;
   } else {
     value = address;
   }
@@ -152,7 +152,7 @@ module_t::~module_t() {
   }
 }
 
-match_result_t module_t::memory_access_match(action_t * const action, operation_t operation, reg_t address, bool has_data, reg_t data)
+match_result_t module_t::memory_access_match(action_t * const action, operation_t operation, reg_t address, std::optional<reg_t> data)
 {
   state_t * const state = proc->get_state();
   if (state->debug_mode)
@@ -172,7 +172,7 @@ match_result_t module_t::memory_access_match(action_t * const action, operation_
      * entire chain did not match. This is allowed by the spec, because the final
      * trigger in the chain will never get `hit` set unless the entire chain
      * matches. */
-    match_result_t result = triggers[i]->memory_access_match(proc, operation, address, has_data, data);
+    match_result_t result = triggers[i]->memory_access_match(proc, operation, address, data);
     if (result != MATCH_NONE && !triggers[i]->chain()) {
       *action = triggers[i]->action;
       return result;
diff --git a/riscv/triggers.h b/riscv/triggers.h
index 05ce75e..7b40b8f 100644
--- a/riscv/triggers.h
+++ b/riscv/triggers.h
@@ -2,6 +2,7 @@
 #define _RISCV_TRIGGERS_H
 
 #include <vector>
+#include <optional>
 
 #include "decode.h"
 
@@ -42,7 +43,7 @@ class matched_t
 class trigger_t {
 public:
   virtual match_result_t memory_access_match(processor_t * const proc,
-      operation_t operation, reg_t address, bool has_data, reg_t data=0) = 0;
+      operation_t operation, reg_t address, std::optional<reg_t> data) = 0;
 
   virtual reg_t tdata1_read(const processor_t * const proc) const noexcept = 0;
   virtual bool tdata1_write(processor_t * const proc, const reg_t val) noexcept = 0;
@@ -87,7 +88,7 @@ public:
   virtual bool load() const override { return load_bit; }
 
   virtual match_result_t memory_access_match(processor_t * const proc,
-      operation_t operation, reg_t address, bool has_data, reg_t data=0) override;
+      operation_t operation, reg_t address, std::optional<reg_t> data) override;
 
 private:
   bool simple_match(unsigned xlen, reg_t value) const;
@@ -114,7 +115,7 @@ public:
   unsigned count() const { return triggers.size(); }
 
   match_result_t memory_access_match(action_t * const action,
-      operation_t operation, reg_t address, bool has_data, reg_t data=0);
+      operation_t operation, reg_t address, std::optional<reg_t> data);
 
   reg_t tdata1_read(const processor_t * const proc, unsigned index) const noexcept;
   bool tdata1_write(processor_t * const proc, unsigned index, const reg_t val) noexcept;