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author | Tim Newsome <tim@sifive.com> | 2022-03-16 10:16:37 -0700 |
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committer | Tim Newsome <tim@sifive.com> | 2022-03-30 10:41:45 -0700 |
commit | 02b3b36901daa3e030af40c71ac2418fc80fd90e (patch) | |
tree | d4e74246cc2c120930aecfbe453a9441f7f909d7 | |
parent | 9bd1f818aee132ca6434e0ecaf168821024b1adc (diff) | |
download | spike-02b3b36901daa3e030af40c71ac2418fc80fd90e.zip spike-02b3b36901daa3e030af40c71ac2418fc80fd90e.tar.gz spike-02b3b36901daa3e030af40c71ac2418fc80fd90e.tar.bz2 |
Move tdata1 write logic into triggers.
-rw-r--r-- | riscv/csrs.cc | 24 | ||||
-rw-r--r-- | riscv/triggers.cc | 25 | ||||
-rw-r--r-- | riscv/triggers.h | 1 |
3 files changed, 27 insertions, 23 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 29cc0fe..34ba699 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -995,29 +995,7 @@ reg_t tdata1_csr_t::read() const noexcept { } bool tdata1_csr_t::unlogged_write(const reg_t val) noexcept { - triggers::mcontrol_t *mc = proc->TM.triggers[state->tselect->read()]; - if (mc->dmode && !state->debug_mode) { - return false; - } - auto xlen = proc->get_xlen(); - mc->dmode = get_field(val, MCONTROL_DMODE(xlen)); - mc->select = get_field(val, MCONTROL_SELECT); - mc->timing = get_field(val, MCONTROL_TIMING); - mc->action = (triggers::action_t) get_field(val, MCONTROL_ACTION); - mc->chain = get_field(val, MCONTROL_CHAIN); - mc->match = (triggers::mcontrol_t::match_t) get_field(val, MCONTROL_MATCH); - mc->m = get_field(val, MCONTROL_M); - mc->h = get_field(val, MCONTROL_H); - mc->s = get_field(val, MCONTROL_S); - mc->u = get_field(val, MCONTROL_U); - mc->execute = get_field(val, MCONTROL_EXECUTE); - mc->store = get_field(val, MCONTROL_STORE); - mc->load = get_field(val, MCONTROL_LOAD); - // Assume we're here because of csrw. - if (mc->execute) - mc->timing = 0; - proc->trigger_updated(); - return true; + return proc->TM.triggers[state->tselect->read()]->tdata1_write(proc, val); } diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 7fb5e8c..527ae71 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -31,6 +31,31 @@ reg_t mcontrol_t::tdata1_read(const processor_t *proc) const noexcept { return v; } +bool mcontrol_t::tdata1_write(processor_t *proc, const reg_t val) noexcept { + if (dmode && !proc->get_state()->debug_mode) { + return false; + } + auto xlen = proc->get_xlen(); + dmode = get_field(val, MCONTROL_DMODE(xlen)); + select = get_field(val, MCONTROL_SELECT); + timing = get_field(val, MCONTROL_TIMING); + action = (triggers::action_t) get_field(val, MCONTROL_ACTION); + chain = get_field(val, MCONTROL_CHAIN); + match = (triggers::mcontrol_t::match_t) get_field(val, MCONTROL_MATCH); + m = get_field(val, MCONTROL_M); + h = get_field(val, MCONTROL_H); + s = get_field(val, MCONTROL_S); + u = get_field(val, MCONTROL_U); + execute = get_field(val, MCONTROL_EXECUTE); + store = get_field(val, MCONTROL_STORE); + load = get_field(val, MCONTROL_LOAD); + // Assume we're here because of csrw. + if (execute) + timing = 0; + proc->trigger_updated(); + return true; +} + module_t::module_t(unsigned count) : triggers(count) { for (unsigned i = 0; i < count; i++) { triggers[i] = new mcontrol_t(); diff --git a/riscv/triggers.h b/riscv/triggers.h index 25fdd66..ac5724b 100644 --- a/riscv/triggers.h +++ b/riscv/triggers.h @@ -45,6 +45,7 @@ public: mcontrol_t(); reg_t tdata1_read(const processor_t *proc) const noexcept; + bool tdata1_write(processor_t *proc, const reg_t val) noexcept; uint8_t type; uint8_t maskmax; |