Merge pull request #1240 from adurbin-rivos/svadu

Add support for Svadu Extension

11 files changed, 17 insertions, 15 deletions

diff --git a/ci-tests/testlib.c b/ci-tests/testlib.c
index f20e749..9343b61 100644
--- a/ci-tests/testlib.c
+++ b/ci-tests/testlib.c
@@ -23,7 +23,6 @@ int main()
             "vlen:128,elen:64",
             false,
             endianness_little,
-            false,
             16,
             mem_cfg,
             hartids,
diff --git a/riscv/cfg.h b/riscv/cfg.h
index a40bbf5..58c792c 100644
--- a/riscv/cfg.h
+++ b/riscv/cfg.h
@@ -67,7 +67,6 @@ public:
         const char *default_varch,
         const bool default_misaligned,
         const endianness_t default_endianness,
-        const bool default_dirty_enabled,
         const reg_t default_pmpregions,
         const std::vector<mem_cfg_t> &default_mem_layout,
         const std::vector<int> default_hartids,
@@ -80,7 +79,6 @@ public:
       varch(default_varch),
       misaligned(default_misaligned),
       endianness(default_endianness),
-      dirty_enabled(default_dirty_enabled),
       pmpregions(default_pmpregions),
       mem_layout(default_mem_layout),
       hartids(default_hartids),
@@ -96,7 +94,6 @@ public:
   cfg_arg_t<const char *>            varch;
   bool                               misaligned;
   endianness_t                       endianness;
-  bool                               dirty_enabled;
   reg_t                              pmpregions;
   cfg_arg_t<std::vector<mem_cfg_t>>  mem_layout;
   std::optional<reg_t>               start_pc;
diff --git a/riscv/csrs.h b/riscv/csrs.h
index 31ba11b..5dab1fc 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -453,12 +453,13 @@ class masked_csr_t: public basic_csr_t {
 
 // henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
 // henvcfg.stce is read_only 0 when menvcfg.stce = 0
+// henvcfg.hade is read_only 0 when menvcfg.hade = 0
 class henvcfg_csr_t final: public masked_csr_t {
  public:
   henvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init, csr_t_p menvcfg);
 
   reg_t read() const noexcept override {
-    return (menvcfg->read() | ~(MENVCFG_PBMTE | MENVCFG_STCE)) & masked_csr_t::read();
+    return (menvcfg->read() | ~(MENVCFG_PBMTE | MENVCFG_STCE | MENVCFG_HADE)) & masked_csr_t::read();
   }
 
   virtual void verify_permissions(insn_t insn, bool write) const override;
diff --git a/riscv/encoding.h b/riscv/encoding.h
index f899a64..725630e 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: BSD-3-Clause */
 
-/* Copyright (c) 2022 RISC-V International */
+/* Copyright (c) 2023 RISC-V International */
 
 /*
  * This file is auto-generated by running 'make' in
- * https://github.com/riscv/riscv-opcodes (4d7f46e)
+ * https://github.com/riscv/riscv-opcodes (ebd4dbf)
  */
 
 #ifndef RISCV_CSR_ENCODING_H
@@ -156,9 +156,11 @@
 #define MENVCFG_CBIE  0x00000030
 #define MENVCFG_CBCFE 0x00000040
 #define MENVCFG_CBZE  0x00000080
+#define MENVCFG_HADE  0x2000000000000000
 #define MENVCFG_PBMTE 0x4000000000000000
 #define MENVCFG_STCE  0x8000000000000000
 
+#define MENVCFGH_HADE  0x20000000
 #define MENVCFGH_PBMTE 0x40000000
 #define MENVCFGH_STCE  0x80000000
 
@@ -191,9 +193,11 @@
 #define HENVCFG_CBIE  0x00000030
 #define HENVCFG_CBCFE 0x00000040
 #define HENVCFG_CBZE  0x00000080
+#define HENVCFG_HADE  0x2000000000000000
 #define HENVCFG_PBMTE 0x4000000000000000
 #define HENVCFG_STCE  0x8000000000000000
 
+#define HENVCFGH_HADE  0x20000000
 #define HENVCFGH_PBMTE 0x40000000
 #define HENVCFGH_STCE  0x80000000
 
diff --git a/riscv/isa_parser.cc b/riscv/isa_parser.cc
index c0cada7..c074975 100644
--- a/riscv/isa_parser.cc
+++ b/riscv/isa_parser.cc
@@ -206,6 +206,8 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
       extension_table[EXT_SMSTATEEN] = true;
     } else if (ext_str == "sscofpmf") {
       extension_table[EXT_SSCOFPMF] = true;
+    } else if (ext_str == "svadu") {
+      extension_table[EXT_SVADU] = true;
     } else if (ext_str == "svnapot") {
       extension_table[EXT_SVNAPOT] = true;
     } else if (ext_str == "svpbmt") {
diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h
index 4be81d8..01f4680 100644
--- a/riscv/isa_parser.h
+++ b/riscv/isa_parser.h
@@ -42,6 +42,7 @@ typedef enum {
   EXT_SMEPMP,
   EXT_SMSTATEEN,
   EXT_SSCOFPMF,
+  EXT_SVADU,
   EXT_SVNAPOT,
   EXT_SVPBMT,
   EXT_SVINVAL,
diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index e5f8a1f..fc80dfa 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -388,6 +388,7 @@ reg_t mmu_t::s2xlate(reg_t gva, reg_t gpa, access_type type, access_type trap_ty
       reg_t pte = pte_load(pte_paddr, gva, virt, trap_type, vm.ptesize);
       reg_t ppn = (pte & ~reg_t(PTE_ATTR)) >> PTE_PPN_SHIFT;
       bool pbmte = proc->get_state()->menvcfg->read() & MENVCFG_PBMTE;
+      bool hade = proc->get_state()->menvcfg->read() & MENVCFG_HADE;
 
       if (pte & PTE_RSVD) {
         break;
@@ -415,7 +416,7 @@ reg_t mmu_t::s2xlate(reg_t gva, reg_t gpa, access_type type, access_type trap_ty
         reg_t ad = PTE_A | ((type == STORE) * PTE_D);
 
         if ((pte & ad) != ad) {
-          if (proc->cfg->dirty_enabled) {
+          if (hade) {
             // set accessed and possibly dirty bits
             pte_store(pte_paddr, pte | ad, gva, virt, type, vm.ptesize);
           } else {
@@ -476,6 +477,7 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode, bool virt, bool hlvx
     reg_t pte = pte_load(pte_paddr, addr, virt, type, vm.ptesize);
     reg_t ppn = (pte & ~reg_t(PTE_ATTR)) >> PTE_PPN_SHIFT;
     bool pbmte = virt ? (proc->get_state()->henvcfg->read() & HENVCFG_PBMTE) : (proc->get_state()->menvcfg->read() & MENVCFG_PBMTE);
+    bool hade = virt ? (proc->get_state()->henvcfg->read() & HENVCFG_HADE) : (proc->get_state()->menvcfg->read() & MENVCFG_HADE);
 
     if (pte & PTE_RSVD) {
       break;
@@ -503,7 +505,7 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode, bool virt, bool hlvx
       reg_t ad = PTE_A | ((type == STORE) * PTE_D);
 
       if ((pte & ad) != ad) {
-        if (proc->cfg->dirty_enabled) {
+        if (hade) {
           // set accessed and possibly dirty bits.
           pte_store(pte_paddr, pte | ad, addr, virt, type, vm.ptesize);
         } else {
diff --git a/riscv/mmu.h b/riscv/mmu.h
index d82f576..8f39047 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -274,8 +274,6 @@ public:
 
   void register_memtracer(memtracer_t*);
 
-  int is_dirty_enabled() { return proc && proc->cfg->dirty_enabled; }
-
   int is_misaligned_enabled()
   {
     return proc && proc->get_cfg().misaligned;
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 27ca995..81ae0ce 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -434,6 +434,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   if (proc->extension_enabled_const('U')) {
     const reg_t menvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? MENVCFG_CBCFE | MENVCFG_CBIE : 0) |
                               (proc->extension_enabled(EXT_ZICBOZ) ? MENVCFG_CBZE : 0) |
+                              (proc->extension_enabled(EXT_SVADU) ? MENVCFG_HADE: 0) |
                               (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0) |
                               (proc->extension_enabled(EXT_SSTC) ? MENVCFG_STCE : 0);
     const reg_t menvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0);
@@ -449,6 +450,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
     csrmap[CSR_SENVCFG] = senvcfg = std::make_shared<senvcfg_csr_t>(proc, CSR_SENVCFG, senvcfg_mask, 0);
     const reg_t henvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? HENVCFG_CBCFE | HENVCFG_CBIE : 0) |
                               (proc->extension_enabled(EXT_ZICBOZ) ? HENVCFG_CBZE : 0) |
+                              (proc->extension_enabled(EXT_SVADU) ? HENVCFG_HADE: 0) |
                               (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0) |
                               (proc->extension_enabled(EXT_SSTC) ? HENVCFG_STCE : 0);
     const reg_t henvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0);
diff --git a/spike_main/spike-log-parser.cc b/spike_main/spike-log-parser.cc
index 0020751..cec9c31 100644
--- a/spike_main/spike-log-parser.cc
+++ b/spike_main/spike-log-parser.cc
@@ -35,7 +35,6 @@ int main(int UNUSED argc, char** argv)
             /*default_varch=*/DEFAULT_VARCH,
             /*default_misaligned=*/false,
             /*default_endianness*/endianness_little,
-            /*default_dirty_enabled=*/false,
             /*default_pmpregions=*/16,
             /*default_mem_layout=*/std::vector<mem_cfg_t>(),
             /*default_hartids=*/std::vector<int>(),
diff --git a/spike_main/spike.cc b/spike_main/spike.cc
index 8669375..9032db4 100644
--- a/spike_main/spike.cc
+++ b/spike_main/spike.cc
@@ -70,7 +70,6 @@ static void help(int exit_code = 1)
   fprintf(stderr, "  --initrd=<path>       Load kernel initrd into memory\n");
   fprintf(stderr, "  --bootargs=<args>     Provide custom bootargs for kernel [default: console=hvc0 earlycon=sbi]\n");
   fprintf(stderr, "  --real-time-clint     Increment clint time at real-time rate\n");
-  fprintf(stderr, "  --mmu-dirty           Enable hardware management of PTE accessed and dirty bits\n");
   fprintf(stderr, "  --triggers=<n>        Number of supported triggers [default 4]\n");
   fprintf(stderr, "  --dm-progsize=<words> Progsize for the debug module [default 2]\n");
   fprintf(stderr, "  --dm-sba=<bits>       Debug system bus access supports up to "
@@ -352,7 +351,6 @@ int main(int argc, char** argv)
             /*default_varch=*/DEFAULT_VARCH,
             /*default_misaligned=*/false,
             /*default_endianness*/endianness_little,
-            /*default_dirty_enabled*/false,
             /*default_pmpregions=*/16,
             /*default_mem_layout=*/parse_mem_layout("2048"),
             /*default_hartids=*/std::vector<int>(),
@@ -440,7 +438,6 @@ int main(int argc, char** argv)
   parser.option(0, "initrd", 1, [&](const char* s){initrd = s;});
   parser.option(0, "bootargs", 1, [&](const char* s){cfg.bootargs = s;});
   parser.option(0, "real-time-clint", 0, [&](const char UNUSED *s){cfg.real_time_clint = true;});
-  parser.option(0, "mmu-dirty", 0, [&](const char UNUSED *s){cfg.dirty_enabled = true;});
   parser.option(0, "triggers", 1, [&](const char *s){cfg.trigger_count = atoul_safe(s);});
   parser.option(0, "extlib", 1, [&](const char *s){
     void *lib = dlopen(s, RTLD_NOW | RTLD_GLOBAL);