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authorPhilipp Tomsich <philipp.tomsich@vrull.eu>2023-01-12 01:19:15 +0100
committerAndrew Waterman <andrew@sifive.com>2023-01-31 09:34:41 -0800
commite69b20645654b498a4fdcd83ff2409037d1a5bf7 (patch)
tree74c8a3f5b7730117b31b284fce05bb1f3e334fef
parentba1e1b62860f58686d0e752b5f6a4079e1d1c22b (diff)
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Zicond: implement Zicond (conditional integer operations)
This implements the Zicond (conditional integer operations) extension, as of version 1.0-draft-20230120. The Zicond extension acts as a building block for branchless sequences including conditional-arithmetic, conditional-logic and conditional-select/move. The following instructions constitute Zicond: - czero.eqz rd, rs1, rs2 => rd = (rs2 == 0) ? 0 : rs1 - czero.nez rd, rs1, rs2 => rd = (rs2 != 0) ? 0 : rs1 See https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230120/riscv-zicond_1.0-draft-20230120.pdf for the proposed specification and usage details.
-rw-r--r--riscv/insns/czero_eqz.h2
-rw-r--r--riscv/insns/czero_nez.h2
-rw-r--r--riscv/isa_parser.cc2
-rw-r--r--riscv/isa_parser.h1
-rw-r--r--riscv/riscv.mk.in5
5 files changed, 12 insertions, 0 deletions
diff --git a/riscv/insns/czero_eqz.h b/riscv/insns/czero_eqz.h
new file mode 100644
index 0000000..24062af
--- /dev/null
+++ b/riscv/insns/czero_eqz.h
@@ -0,0 +1,2 @@
+require_extension(EXT_ZICOND);
+WRITE_RD(RS2 == 0 ? 0 : RS1);
diff --git a/riscv/insns/czero_nez.h b/riscv/insns/czero_nez.h
new file mode 100644
index 0000000..cd6c8af
--- /dev/null
+++ b/riscv/insns/czero_nez.h
@@ -0,0 +1,2 @@
+require_extension(EXT_ZICOND);
+WRITE_RD(RS2 != 0 ? 0 : RS1);
diff --git a/riscv/isa_parser.cc b/riscv/isa_parser.cc
index c074975..00178ea 100644
--- a/riscv/isa_parser.cc
+++ b/riscv/isa_parser.cc
@@ -220,6 +220,8 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
extension_table[EXT_ZICBOZ] = true;
} else if (ext_str == "zicbop") {
} else if (ext_str == "zicntr") {
+ } else if (ext_str == "zicond") {
+ extension_table[EXT_ZICOND] = true;
} else if (ext_str == "zihpm") {
} else if (ext_str == "sstc") {
extension_table[EXT_SSTC] = true;
diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h
index 01f4680..3ae9a16 100644
--- a/riscv/isa_parser.h
+++ b/riscv/isa_parser.h
@@ -53,6 +53,7 @@ typedef enum {
EXT_ZICBOM,
EXT_ZICBOZ,
EXT_ZICNTR,
+ EXT_ZICOND,
EXT_ZIHPM,
EXT_XZBP,
EXT_XZBS,
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 6e40569..a1540d4 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -1305,6 +1305,10 @@ riscv_insn_ext_cmo = \
cbo_inval \
cbo_zero \
+riscv_insn_ext_zicond = \
+ czero_eqz \
+ czero_nez \
+
riscv_insn_list = \
$(riscv_insn_ext_a) \
$(riscv_insn_ext_c) \
@@ -1323,6 +1327,7 @@ riscv_insn_list = \
$(riscv_insn_priv) \
$(riscv_insn_svinval) \
$(riscv_insn_ext_cmo) \
+ $(riscv_insn_ext_zicond) \
riscv_gen_srcs = $(addsuffix .cc,$(riscv_insn_list))