Merge pull request #1241 from riscv-software-src/zicond

Implement Zicond (conditional integer operations)

6 files changed, 93 insertions, 2 deletions

diff --git a/riscv/encoding.h b/riscv/encoding.h
index 725630e..ef70f5a 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -4,7 +4,7 @@
 
 /*
  * This file is auto-generated by running 'make' in
- * https://github.com/riscv/riscv-opcodes (ebd4dbf)
+ * https://github.com/riscv/riscv-opcodes (87a8824)
  */
 
 #ifndef RISCV_CSR_ENCODING_H
@@ -713,6 +713,10 @@
 #define MASK_CTZ 0xfff0707f
 #define MATCH_CTZW 0x6010101b
 #define MASK_CTZW 0xfff0707f
+#define MATCH_CZERO_EQZ 0xe005033
+#define MASK_CZERO_EQZ 0xfe00707f
+#define MATCH_CZERO_NEZ 0xe007033
+#define MASK_CZERO_NEZ 0xfe00707f
 #define MATCH_DIV 0x2004033
 #define MASK_DIV 0xfe00707f
 #define MATCH_DIVU 0x2005033
@@ -1519,6 +1523,8 @@
 #define MASK_SLLI32 0xfe00707f
 #define MATCH_SLLI8 0x7c000077
 #define MASK_SLLI8 0xff80707f
+#define MATCH_SLLI_RV32 0x1013
+#define MASK_SLLI_RV32 0xfe00707f
 #define MATCH_SLLI_UW 0x800101b
 #define MASK_SLLI_UW 0xfc00707f
 #define MATCH_SLLIW 0x101b
@@ -1663,6 +1669,8 @@
 #define MASK_SRAI8 0xff80707f
 #define MATCH_SRAI8_U 0x78800077
 #define MASK_SRAI8_U 0xff80707f
+#define MATCH_SRAI_RV32 0x40005013
+#define MASK_SRAI_RV32 0xfe00707f
 #define MATCH_SRAI_U 0xd4001077
 #define MASK_SRAI_U 0xfc00707f
 #define MATCH_SRAIW 0x4000501b
@@ -1701,6 +1709,8 @@
 #define MASK_SRLI8 0xff80707f
 #define MATCH_SRLI8_U 0x7a800077
 #define MASK_SRLI8_U 0xff80707f
+#define MATCH_SRLI_RV32 0x5013
+#define MASK_SRLI_RV32 0xfe00707f
 #define MATCH_SRLIW 0x501b
 #define MASK_SRLIW 0xfe00707f
 #define MATCH_SRLW 0x503b
@@ -2863,6 +2873,9 @@
 #define CSR_STVAL 0x143
 #define CSR_SIP 0x144
 #define CSR_STIMECMP 0x14d
+#define CSR_SISELECT 0x150
+#define CSR_SIREG 0x151
+#define CSR_STOPEI 0x15c
 #define CSR_SATP 0x180
 #define CSR_SCONTEXT 0x5a8
 #define CSR_VSSTATUS 0x200
@@ -2874,6 +2887,9 @@
 #define CSR_VSTVAL 0x243
 #define CSR_VSIP 0x244
 #define CSR_VSTIMECMP 0x24d
+#define CSR_VSISELECT 0x250
+#define CSR_VSIREG 0x251
+#define CSR_VSTOPEI 0x25c
 #define CSR_VSATP 0x280
 #define CSR_HSTATUS 0x600
 #define CSR_HEDELEG 0x602
@@ -2882,6 +2898,8 @@
 #define CSR_HTIMEDELTA 0x605
 #define CSR_HCOUNTEREN 0x606
 #define CSR_HGEIE 0x607
+#define CSR_HVIEN 0x608
+#define CSR_HVICTL 0x609
 #define CSR_HENVCFG 0x60a
 #define CSR_HSTATEEN0 0x60c
 #define CSR_HSTATEEN1 0x60d
@@ -2890,11 +2908,15 @@
 #define CSR_HTVAL 0x643
 #define CSR_HIP 0x644
 #define CSR_HVIP 0x645
+#define CSR_HVIPRIO1 0x646
+#define CSR_HVIPRIO2 0x647
 #define CSR_HTINST 0x64a
 #define CSR_HGATP 0x680
 #define CSR_HCONTEXT 0x6a8
 #define CSR_HGEIP 0xe12
+#define CSR_VSTOPI 0xeb0
 #define CSR_SCOUNTOVF 0xda0
+#define CSR_STOPI 0xdb0
 #define CSR_UTVT 0x7
 #define CSR_UNXTI 0x45
 #define CSR_UINTSTATUS 0x46
@@ -2917,6 +2939,8 @@
 #define CSR_MIE 0x304
 #define CSR_MTVEC 0x305
 #define CSR_MCOUNTEREN 0x306
+#define CSR_MVIEN 0x308
+#define CSR_MVIP 0x309
 #define CSR_MENVCFG 0x30a
 #define CSR_MSTATEEN0 0x30c
 #define CSR_MSTATEEN1 0x30d
@@ -2930,6 +2954,9 @@
 #define CSR_MIP 0x344
 #define CSR_MTINST 0x34a
 #define CSR_MTVAL2 0x34b
+#define CSR_MISELECT 0x350
+#define CSR_MIREG 0x351
+#define CSR_MTOPEI 0x35c
 #define CSR_PMPCFG0 0x3a0
 #define CSR_PMPCFG1 0x3a1
 #define CSR_PMPCFG2 0x3a2
@@ -3088,10 +3115,20 @@
 #define CSR_MIMPID 0xf13
 #define CSR_MHARTID 0xf14
 #define CSR_MCONFIGPTR 0xf15
+#define CSR_MTOPI 0xfb0
+#define CSR_SIEH 0x114
+#define CSR_SIPH 0x154
 #define CSR_STIMECMPH 0x15d
+#define CSR_VSIEH 0x214
+#define CSR_VSIPH 0x254
 #define CSR_VSTIMECMPH 0x25d
 #define CSR_HTIMEDELTAH 0x615
+#define CSR_HIDELEGH 0x613
+#define CSR_HVIENH 0x618
 #define CSR_HENVCFGH 0x61a
+#define CSR_HVIPH 0x655
+#define CSR_HVIPRIO1H 0x656
+#define CSR_HVIPRIO2H 0x657
 #define CSR_HSTATEEN0H 0x61c
 #define CSR_HSTATEEN1H 0x61d
 #define CSR_HSTATEEN2H 0x61e
@@ -3129,11 +3166,16 @@
 #define CSR_HPMCOUNTER30H 0xc9e
 #define CSR_HPMCOUNTER31H 0xc9f
 #define CSR_MSTATUSH 0x310
+#define CSR_MIDELEGH 0x313
+#define CSR_MIEH 0x314
+#define CSR_MVIENH 0x318
+#define CSR_MVIPH 0x319
 #define CSR_MENVCFGH 0x31a
 #define CSR_MSTATEEN0H 0x31c
 #define CSR_MSTATEEN1H 0x31d
 #define CSR_MSTATEEN2H 0x31e
 #define CSR_MSTATEEN3H 0x31f
+#define CSR_MIPH 0x354
 #define CSR_MHPMEVENT3H 0x723
 #define CSR_MHPMEVENT4H 0x724
 #define CSR_MHPMEVENT5H 0x725
@@ -3239,7 +3281,7 @@
 #define INSN_FIELD_IMM12LO 0xf80
 #define INSN_FIELD_BIMM12LO 0xf80
 #define INSN_FIELD_ZIMM 0xf8000
-#define INSN_FIELD_SHAMT 0x7f00000
+#define INSN_FIELD_SHAMTQ 0x7f00000
 #define INSN_FIELD_SHAMTW 0x1f00000
 #define INSN_FIELD_SHAMTW4 0xf00000
 #define INSN_FIELD_SHAMTD 0x3f00000
@@ -3489,6 +3531,8 @@ DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
 DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
 DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
 DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW)
+DECLARE_INSN(czero_eqz, MATCH_CZERO_EQZ, MASK_CZERO_EQZ)
+DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ)
 DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
 DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
 DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
@@ -3892,6 +3936,7 @@ DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
 DECLARE_INSN(slli16, MATCH_SLLI16, MASK_SLLI16)
 DECLARE_INSN(slli32, MATCH_SLLI32, MASK_SLLI32)
 DECLARE_INSN(slli8, MATCH_SLLI8, MASK_SLLI8)
+DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
 DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
 DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
 DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
@@ -3964,6 +4009,7 @@ DECLARE_INSN(srai32, MATCH_SRAI32, MASK_SRAI32)
 DECLARE_INSN(srai32_u, MATCH_SRAI32_U, MASK_SRAI32_U)
 DECLARE_INSN(srai8, MATCH_SRAI8, MASK_SRAI8)
 DECLARE_INSN(srai8_u, MATCH_SRAI8_U, MASK_SRAI8_U)
+DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
 DECLARE_INSN(srai_u, MATCH_SRAI_U, MASK_SRAI_U)
 DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
 DECLARE_INSN(sraiw_u, MATCH_SRAIW_U, MASK_SRAIW_U)
@@ -3983,6 +4029,7 @@ DECLARE_INSN(srli32, MATCH_SRLI32, MASK_SRLI32)
 DECLARE_INSN(srli32_u, MATCH_SRLI32_U, MASK_SRLI32_U)
 DECLARE_INSN(srli8, MATCH_SRLI8, MASK_SRLI8)
 DECLARE_INSN(srli8_u, MATCH_SRLI8_U, MASK_SRLI8_U)
+DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
 DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
 DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
 DECLARE_INSN(sro, MATCH_SRO, MASK_SRO)
@@ -4596,6 +4643,9 @@ DECLARE_CSR(scause, CSR_SCAUSE)
 DECLARE_CSR(stval, CSR_STVAL)
 DECLARE_CSR(sip, CSR_SIP)
 DECLARE_CSR(stimecmp, CSR_STIMECMP)
+DECLARE_CSR(siselect, CSR_SISELECT)
+DECLARE_CSR(sireg, CSR_SIREG)
+DECLARE_CSR(stopei, CSR_STOPEI)
 DECLARE_CSR(satp, CSR_SATP)
 DECLARE_CSR(scontext, CSR_SCONTEXT)
 DECLARE_CSR(vsstatus, CSR_VSSTATUS)
@@ -4607,6 +4657,9 @@ DECLARE_CSR(vscause, CSR_VSCAUSE)
 DECLARE_CSR(vstval, CSR_VSTVAL)
 DECLARE_CSR(vsip, CSR_VSIP)
 DECLARE_CSR(vstimecmp, CSR_VSTIMECMP)
+DECLARE_CSR(vsiselect, CSR_VSISELECT)
+DECLARE_CSR(vsireg, CSR_VSIREG)
+DECLARE_CSR(vstopei, CSR_VSTOPEI)
 DECLARE_CSR(vsatp, CSR_VSATP)
 DECLARE_CSR(hstatus, CSR_HSTATUS)
 DECLARE_CSR(hedeleg, CSR_HEDELEG)
@@ -4615,6 +4668,8 @@ DECLARE_CSR(hie, CSR_HIE)
 DECLARE_CSR(htimedelta, CSR_HTIMEDELTA)
 DECLARE_CSR(hcounteren, CSR_HCOUNTEREN)
 DECLARE_CSR(hgeie, CSR_HGEIE)
+DECLARE_CSR(hvien, CSR_HVIEN)
+DECLARE_CSR(hvictl, CSR_HVICTL)
 DECLARE_CSR(henvcfg, CSR_HENVCFG)
 DECLARE_CSR(hstateen0, CSR_HSTATEEN0)
 DECLARE_CSR(hstateen1, CSR_HSTATEEN1)
@@ -4623,11 +4678,15 @@ DECLARE_CSR(hstateen3, CSR_HSTATEEN3)
 DECLARE_CSR(htval, CSR_HTVAL)
 DECLARE_CSR(hip, CSR_HIP)
 DECLARE_CSR(hvip, CSR_HVIP)
+DECLARE_CSR(hviprio1, CSR_HVIPRIO1)
+DECLARE_CSR(hviprio2, CSR_HVIPRIO2)
 DECLARE_CSR(htinst, CSR_HTINST)
 DECLARE_CSR(hgatp, CSR_HGATP)
 DECLARE_CSR(hcontext, CSR_HCONTEXT)
 DECLARE_CSR(hgeip, CSR_HGEIP)
+DECLARE_CSR(vstopi, CSR_VSTOPI)
 DECLARE_CSR(scountovf, CSR_SCOUNTOVF)
+DECLARE_CSR(stopi, CSR_STOPI)
 DECLARE_CSR(utvt, CSR_UTVT)
 DECLARE_CSR(unxti, CSR_UNXTI)
 DECLARE_CSR(uintstatus, CSR_UINTSTATUS)
@@ -4650,6 +4709,8 @@ DECLARE_CSR(mideleg, CSR_MIDELEG)
 DECLARE_CSR(mie, CSR_MIE)
 DECLARE_CSR(mtvec, CSR_MTVEC)
 DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
+DECLARE_CSR(mvien, CSR_MVIEN)
+DECLARE_CSR(mvip, CSR_MVIP)
 DECLARE_CSR(menvcfg, CSR_MENVCFG)
 DECLARE_CSR(mstateen0, CSR_MSTATEEN0)
 DECLARE_CSR(mstateen1, CSR_MSTATEEN1)
@@ -4663,6 +4724,9 @@ DECLARE_CSR(mtval, CSR_MTVAL)
 DECLARE_CSR(mip, CSR_MIP)
 DECLARE_CSR(mtinst, CSR_MTINST)
 DECLARE_CSR(mtval2, CSR_MTVAL2)
+DECLARE_CSR(miselect, CSR_MISELECT)
+DECLARE_CSR(mireg, CSR_MIREG)
+DECLARE_CSR(mtopei, CSR_MTOPEI)
 DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)
 DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)
 DECLARE_CSR(pmpcfg2, CSR_PMPCFG2)
@@ -4821,10 +4885,20 @@ DECLARE_CSR(marchid, CSR_MARCHID)
 DECLARE_CSR(mimpid, CSR_MIMPID)
 DECLARE_CSR(mhartid, CSR_MHARTID)
 DECLARE_CSR(mconfigptr, CSR_MCONFIGPTR)
+DECLARE_CSR(mtopi, CSR_MTOPI)
+DECLARE_CSR(sieh, CSR_SIEH)
+DECLARE_CSR(siph, CSR_SIPH)
 DECLARE_CSR(stimecmph, CSR_STIMECMPH)
+DECLARE_CSR(vsieh, CSR_VSIEH)
+DECLARE_CSR(vsiph, CSR_VSIPH)
 DECLARE_CSR(vstimecmph, CSR_VSTIMECMPH)
 DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH)
+DECLARE_CSR(hidelegh, CSR_HIDELEGH)
+DECLARE_CSR(hvienh, CSR_HVIENH)
 DECLARE_CSR(henvcfgh, CSR_HENVCFGH)
+DECLARE_CSR(hviph, CSR_HVIPH)
+DECLARE_CSR(hviprio1h, CSR_HVIPRIO1H)
+DECLARE_CSR(hviprio2h, CSR_HVIPRIO2H)
 DECLARE_CSR(hstateen0h, CSR_HSTATEEN0H)
 DECLARE_CSR(hstateen1h, CSR_HSTATEEN1H)
 DECLARE_CSR(hstateen2h, CSR_HSTATEEN2H)
@@ -4862,11 +4936,16 @@ DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
 DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
 DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
 DECLARE_CSR(mstatush, CSR_MSTATUSH)
+DECLARE_CSR(midelegh, CSR_MIDELEGH)
+DECLARE_CSR(mieh, CSR_MIEH)
+DECLARE_CSR(mvienh, CSR_MVIENH)
+DECLARE_CSR(mviph, CSR_MVIPH)
 DECLARE_CSR(menvcfgh, CSR_MENVCFGH)
 DECLARE_CSR(mstateen0h, CSR_MSTATEEN0H)
 DECLARE_CSR(mstateen1h, CSR_MSTATEEN1H)
 DECLARE_CSR(mstateen2h, CSR_MSTATEEN2H)
 DECLARE_CSR(mstateen3h, CSR_MSTATEEN3H)
+DECLARE_CSR(miph, CSR_MIPH)
 DECLARE_CSR(mhpmevent3h, CSR_MHPMEVENT3H)
 DECLARE_CSR(mhpmevent4h, CSR_MHPMEVENT4H)
 DECLARE_CSR(mhpmevent5h, CSR_MHPMEVENT5H)
diff --git a/riscv/insns/czero_eqz.h b/riscv/insns/czero_eqz.h
new file mode 100644
index 0000000..24062af
--- /dev/null
+++ b/riscv/insns/czero_eqz.h
@@ -0,0 +1,2 @@
+require_extension(EXT_ZICOND);
+WRITE_RD(RS2 == 0 ? 0 : RS1);
diff --git a/riscv/insns/czero_nez.h b/riscv/insns/czero_nez.h
new file mode 100644
index 0000000..cd6c8af
--- /dev/null
+++ b/riscv/insns/czero_nez.h
@@ -0,0 +1,2 @@
+require_extension(EXT_ZICOND);
+WRITE_RD(RS2 != 0 ? 0 : RS1);
diff --git a/riscv/isa_parser.cc b/riscv/isa_parser.cc
index c074975..00178ea 100644
--- a/riscv/isa_parser.cc
+++ b/riscv/isa_parser.cc
@@ -220,6 +220,8 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
       extension_table[EXT_ZICBOZ] = true;
     } else if (ext_str == "zicbop") {
     } else if (ext_str == "zicntr") {
+    } else if (ext_str == "zicond") {
+      extension_table[EXT_ZICOND] = true;
     } else if (ext_str == "zihpm") {
     } else if (ext_str == "sstc") {
         extension_table[EXT_SSTC] = true;
diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h
index 01f4680..3ae9a16 100644
--- a/riscv/isa_parser.h
+++ b/riscv/isa_parser.h
@@ -53,6 +53,7 @@ typedef enum {
   EXT_ZICBOM,
   EXT_ZICBOZ,
   EXT_ZICNTR,
+  EXT_ZICOND,
   EXT_ZIHPM,
   EXT_XZBP,
   EXT_XZBS,
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 6e40569..a1540d4 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -1305,6 +1305,10 @@ riscv_insn_ext_cmo = \
 	cbo_inval \
 	cbo_zero \
 
+riscv_insn_ext_zicond = \
+        czero_eqz \
+        czero_nez \
+
 riscv_insn_list = \
 	$(riscv_insn_ext_a) \
 	$(riscv_insn_ext_c) \
@@ -1323,6 +1327,7 @@ riscv_insn_list = \
 	$(riscv_insn_priv) \
 	$(riscv_insn_svinval) \
 	$(riscv_insn_ext_cmo) \
+	$(riscv_insn_ext_zicond) \
 
 riscv_gen_srcs = $(addsuffix .cc,$(riscv_insn_list))