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| author | Aaron Durbin <adurbin@rivosinc.com> | 2023-01-27 10:32:26 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@rivosinc.com> | 2023-01-27 10:35:40 -0800 |
| commit | 7ccd0fd3002b297d8bda4b4cd1ec2a6b7987111c (patch) | |
| tree | 5b044dc8c64fcebf68c1b5f98d0a1dbb74e4dbdc | |
| parent | 53222130f60b2d651970a23a60b4f3ab86731ba5 (diff) | |
| download | spike-7ccd0fd3002b297d8bda4b4cd1ec2a6b7987111c.zip spike-7ccd0fd3002b297d8bda4b4cd1ec2a6b7987111c.tar.gz spike-7ccd0fd3002b297d8bda4b4cd1ec2a6b7987111c.tar.bz2 | |
Enable Svadu control bits in menvcfg and henvcfg
Add in the support for the HADE fields in menvcfg and henvcfg
based off of the svadu ISA string. This only allows for the writable
HADE bits being exposed when the svadu ISA string is employed. No
other behavior is implemented.
| -rw-r--r-- | riscv/csrs.h | 3 | ||||
| -rw-r--r-- | riscv/processor.cc | 2 |
2 files changed, 4 insertions, 1 deletions
diff --git a/riscv/csrs.h b/riscv/csrs.h index 31ba11b..5dab1fc 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -453,12 +453,13 @@ class masked_csr_t: public basic_csr_t { // henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0 // henvcfg.stce is read_only 0 when menvcfg.stce = 0 +// henvcfg.hade is read_only 0 when menvcfg.hade = 0 class henvcfg_csr_t final: public masked_csr_t { public: henvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init, csr_t_p menvcfg); reg_t read() const noexcept override { - return (menvcfg->read() | ~(MENVCFG_PBMTE | MENVCFG_STCE)) & masked_csr_t::read(); + return (menvcfg->read() | ~(MENVCFG_PBMTE | MENVCFG_STCE | MENVCFG_HADE)) & masked_csr_t::read(); } virtual void verify_permissions(insn_t insn, bool write) const override; diff --git a/riscv/processor.cc b/riscv/processor.cc index 27ca995..81ae0ce 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -434,6 +434,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa) if (proc->extension_enabled_const('U')) { const reg_t menvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? MENVCFG_CBCFE | MENVCFG_CBIE : 0) | (proc->extension_enabled(EXT_ZICBOZ) ? MENVCFG_CBZE : 0) | + (proc->extension_enabled(EXT_SVADU) ? MENVCFG_HADE: 0) | (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0) | (proc->extension_enabled(EXT_SSTC) ? MENVCFG_STCE : 0); const reg_t menvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0); @@ -449,6 +450,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa) csrmap[CSR_SENVCFG] = senvcfg = std::make_shared<senvcfg_csr_t>(proc, CSR_SENVCFG, senvcfg_mask, 0); const reg_t henvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? HENVCFG_CBCFE | HENVCFG_CBIE : 0) | (proc->extension_enabled(EXT_ZICBOZ) ? HENVCFG_CBZE : 0) | + (proc->extension_enabled(EXT_SVADU) ? HENVCFG_HADE: 0) | (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0) | (proc->extension_enabled(EXT_SSTC) ? HENVCFG_STCE : 0); const reg_t henvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0); |