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author | Andrew Waterman <andrew@sifive.com> | 2023-12-06 23:50:19 -0800 |
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committer | GitHub <noreply@github.com> | 2023-12-06 23:50:19 -0800 |
commit | d94fe56b4fbc000d24f68597eb32e13cb73802ef (patch) | |
tree | d0acb01d2a4c3dc9445d32b7b1229b09a9f9d04a | |
parent | e46586e2b5744c631e4fefede8df9f0108f06b8d (diff) | |
parent | bdfbd54959b31575e410e2267c12b59b0c9917ae (diff) | |
download | spike-d94fe56b4fbc000d24f68597eb32e13cb73802ef.zip spike-d94fe56b4fbc000d24f68597eb32e13cb73802ef.tar.gz spike-d94fe56b4fbc000d24f68597eb32e13cb73802ef.tar.bz2 |
Merge pull request #1523 from YenHaoChen/patch-1
miselect: support miselect when enabling smcsrind
-rw-r--r-- | riscv/processor.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 0ac6e67..5a43d56 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -535,14 +535,14 @@ void state_t::reset(processor_t* const proc, reg_t max_isa) // Smcsrind / Sscsrind - csr_t_p miselect; - csr_t_p siselect; - csr_t_p vsiselect; sscsrind_reg_csr_t::sscsrind_reg_csr_t_p mireg[6]; sscsrind_reg_csr_t::sscsrind_reg_csr_t_p sireg[6]; sscsrind_reg_csr_t::sscsrind_reg_csr_t_p vsireg[6]; if (proc->extension_enabled_const(EXT_SMCSRIND)) { + csr_t_p miselect = std::make_shared<basic_csr_t>(proc, CSR_MISELECT, 0); + csrmap[CSR_MISELECT] = miselect; + const reg_t mireg_csrs[] = { CSR_MIREG, CSR_MIREG2, CSR_MIREG3, CSR_MIREG4, CSR_MIREG5, CSR_MIREG6 }; auto i = 0; for (auto csr : mireg_csrs) { @@ -552,9 +552,9 @@ void state_t::reset(processor_t* const proc, reg_t max_isa) } if (proc->extension_enabled_const(EXT_SSCSRIND)) { - vsiselect = std::make_shared<basic_csr_t>(proc, CSR_VSISELECT, 0); + csr_t_p vsiselect = std::make_shared<basic_csr_t>(proc, CSR_VSISELECT, 0); csrmap[CSR_VSISELECT] = vsiselect; - siselect = std::make_shared<basic_csr_t>(proc, CSR_SISELECT, 0); + csr_t_p siselect = std::make_shared<basic_csr_t>(proc, CSR_SISELECT, 0); csrmap[CSR_SISELECT] = std::make_shared<virtualized_csr_t>(proc, siselect, vsiselect); const reg_t vsireg_csrs[] = { CSR_VSIREG, CSR_VSIREG2, CSR_VSIREG3, CSR_VSIREG4, CSR_VSIREG5, CSR_VSIREG6 }; |