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| author | Tim Newsome <tim@sifive.com> | 2017-09-12 11:04:08 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-09-12 11:04:08 -0700 |
| commit | fb1f3f7ca99d2d1c0ee0b602a2b4b1ef218bf49a (patch) | |
| tree | 29c3e6e7fdfdffbbe50c72c2017249acc65054d9 | |
| parent | 111dce1919d5d4d8bb99673f177add3504d8e9b7 (diff) | |
| download | spike-fb1f3f7ca99d2d1c0ee0b602a2b4b1ef218bf49a.zip spike-fb1f3f7ca99d2d1c0ee0b602a2b4b1ef218bf49a.tar.gz spike-fb1f3f7ca99d2d1c0ee0b602a2b4b1ef218bf49a.tar.bz2 | |
Don't take interrupts while in Debug Mode.
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 00eccc8..b9fbe0e 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -174,7 +174,7 @@ void processor_t::take_interrupt(reg_t pending_interrupts) if (enabled_interrupts == 0) enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled; - if (enabled_interrupts) + if (state.dcsr.cause == 0 && enabled_interrupts) throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts)); } |