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| author | Tim Newsome <tim@sifive.com> | 2017-09-21 12:42:20 -0700 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2017-09-21 12:42:20 -0700 |
| commit | b86f2a51f522f020ad0d90f598f4c501f41da232 (patch) | |
| tree | 2c466d6f2c5a8a22f266d607f6e95b95f8dcc33a | |
| parent | c471f5d84e2fc27e3eb4c2997635d3f2c83d7818 (diff) | |
| download | spike-b86f2a51f522f020ad0d90f598f4c501f41da232.zip spike-b86f2a51f522f020ad0d90f598f4c501f41da232.tar.gz spike-b86f2a51f522f020ad0d90f598f4c501f41da232.tar.bz2 | |
Fix corner case in repeated execution (#127)
Specifically, don't print out the execution count if the same
instruction is executed by different harts.
| -rw-r--r-- | riscv/processor.cc | 5 | ||||
| -rw-r--r-- | riscv/processor.h | 3 |
2 files changed, 4 insertions, 4 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index b9fbe0e..6804ba7 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -22,7 +22,7 @@ processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id, bool halt_on_reset) : debug(false), halt_request(false), sim(sim), ext(NULL), id(id), - halt_on_reset(halt_on_reset) + halt_on_reset(halt_on_reset), last_pc(1), executions(1) { parse_isa_string(isa); register_base_instructions(); @@ -274,9 +274,6 @@ void processor_t::take_trap(trap_t& t, reg_t epc) void processor_t::disasm(insn_t insn) { - static uint64_t last_pc = 1, last_bits; - static uint64_t executions = 1; - uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1); if (last_pc != state.pc || last_bits != bits) { if (executions != 1) { diff --git a/riscv/processor.h b/riscv/processor.h index 6e8d684..2d82d91 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -316,6 +316,9 @@ private: void build_opcode_map(); void register_base_instructions(); insn_func_t decode_insn(insn_t insn); + + // Track repeated executions for processor_t::disasm() + uint64_t last_pc, last_bits, executions; }; reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc); |